‘DARE takes the ambition for self-sufficiency in software-hardware technology to a new level’

Following a tumultuous period of intensifying geopolitical competition – with numerous reports, from Draghi to Heitor, casting a critical eye over the state of European competitiveness – Europe’s need for technological autonomy has come into ever-clearer focus. ‘It has become increasingly apparent that Europe’s dependence on external supply chains for critical technology such as semiconductors poses a series of risks,’ Vanessa Iglesias, EU projects innovation manager at BSC, notes. ‘These risks range from restricted access to the latest generation of technologies to consequences for cybersecurity, data protection, trade secrets, and data ownership, for example.’

The quest for European technological sovereignty is not new, however. As John Goodacre (UKRI) and Filippo Mantovani (BSC) noted in their respective interviews for HiPEACinfo 74, prior to 2016’s acquisition of Arm by Softbank, European efforts focused on Arm for technological sovereignty. In the domain of HPC, the Mont-Blanc project, which started in 2011, successfully demonstrated that Arm cores could be used for HPC. Almost a decade after Mont-Blanc began, the Fugaku supercomputer in Japan provided real-life proof of the viability of this approach.

Complementing work undertaken on Arm architectures, RISC-V emerged as an attractive route for sovereign European technology development, given its open-source nature. Multiple projects have been funded by the European High-Performance Computing Joint Undertaking (EuroHPC JU) to create a designed-in-Europe processor and accelerators, and to build out the ecosystems underpinning the deployment of this hardware, including the European Processor Initiative (EPI), EUPILOT, eProcessor, EUPEX, MEEP, and DEEP-SEA.

With €120 million in funding from the EuroHPC JU, an amount which will be matched by co-funding provided by participating states, DARE is a major initiative to further advance made-in-Europe hardware for HPC and AI. ‘DARE is the continuation of an effort for Europe to be self-sufficient in software-hardware technology from top to bottom that started many years ago,’ explains Osman Ünsal, manager of the Computer Architecture for Parallel Paradigms at BSC and the principal investigator of DARE. ‘Building on work undertaken in previous projects, DARE takes the ambition for self-sufficiency to a new level.’

Members of the DARE consortium at the project kickoff in March 2025

Chiplet design

One of the things which marks out DARE from its predecessors is the incorporation of chiplet research. ‘There have been chiplet research projects in the past, but DARE is novel thanks to its combination of RISC-V and a go-to-fab agenda,’ says Osman. The project will develop chiplets for HPC / AI, designed and implemented in Europe.

While NVIDIA is the acknowledged leader in semiconductors for high-performance computing (HPC), the RISC-V HPC ecosystem is being built out and momentum is growing, says Osman. ‘The strength of RISC-V for Europe is that, as an open instruction set architecture (ISA), it promotes inclusivity: anyone can come in and play.’

The project aims to deliver, in Osman’s words, ‘the first mix-and-match chiplet design with designed-in-Europe technology’. Participants in DARE will design, develop and tape out three industry-standard RISC-V-based chiplets, to be fabricated at advanced technology nodes (TSMC 7nm or below).

The design of each of these chiplets will be led by an industry partner, as follows:

• A general-purpose processor, optimized for priority workloads for Europe, including in the areas of health, climate modelling, and energy solutions. This work will be led by processor-solutions provider Codasip, which is headquartered in Munich with design centres in Brno, Prague, Villeneuve-Loubet, Munich, Heraklion, Thessaloniki, Marousi, Barcelona, Bristol, Cambridge, and London.
• A vector accelerator for high-precision HPC tasks and applications merging HPC and AI. This will be led by Openchip, which is headquartered in Barcelona, with offices in Gdańsk, Rome, and Ghent. ‘Unlike graphics processing units (GPUs), this accelerator can self-host – it doesn’t need a core central processing unit (CPU) to boot the operating system and so forth,’ says Osman. ‘It is a more general processor than a GPU and, as such, will require less effort on the part of HPC domain experts to modify their applications.’
• An AI processing unit specifically designed for accelerating AI inference within HPC applications. This work will be led by Axelera AI, whose chief executive is HiPEAC member Fabrizio Del Maffeo and whose chief technology officer is HiPEAC member Evangelos Eleftheriou. Axelera’s advisory board includes HiPEAC members Luca Benini and Marian Verhelst, and its board of directors includes HiPEAC member Massimo Vanzi. Axelera AI is headquartered in Eindoven, with offices in Leuven, Zürich, Bristol and Milan and operations in 15 European countries.

The project will also develop a full HPC and AI software stack (compilers, libraries, operating system, tools), optimized for DARE hardware, to support applications which are viewed as a priority for Europe – for example in the areas of energy, health and climate modelling. By using a hardware-software co-design methodology – something long championed by Osman – DARE will ensure that the hardware is exploited to the maximum while ensuring programmability. Jülich Supercomputing Centre and BSC will act as technical leads for shared applications and software, while imec will serve as technical lead for integration and prototyping.

The development of these processors and accelerators, along with their associated software, aims to strengthen the European HPC ecosystem and define a roadmap for future HPC systems based on made-in-Europe technology. This goes to the heart of the project’s aim to address Europe’s deficit in digital autonomy.

Technical challenges

The project team is closely involved with the development of the RISC-V standard, for example by participating in the working groups on security, vectorization and fault tolerance. ‘The whole DARE landscape is standardized; for example, partners are working on error reporting with the new standard on fault tolerance,’ Osman notes. ‘Others are working on the vector standard, and the RISC-V vector C intrinsics has recently been approved.’ With members of the DARE team, such as Roger Ferrer at BSC, having already worked on this as part of the EPI, the project is therefore helping to shape the standards, not just following them. ‘Because the standard is open, everyone can see these updates immediately and can collaborate or compete on an equal footing,’ Osman adds. ‘We need to be champions of the RISC-V standard, and it is crucial that Europe continues to maintain it in future.’

Along the way, DARE will need to overcome a number of technical challenges. As always, delivering high performance on a low power budget is paramount for ever-more demanding HPC and AI systems. The project team will also have to tackle chiplet integration while building out an emerging software ecosystem. They will have to address advanced node manufacturing and tape-out, an area in which Europe has less experience than other world regions, while keeping pace with the frantic pace of AI.

Coordinating partners and IP

With a consortium of 38 partners and seven affiliated organizations, DARE clearly poses enormous challenges on the project management front as well as the technical side. Yet there are advantages to a large, geographically distributed consortium in a major EU project, according to Osman: ‘Having so many partners in the project builds resilience into the project. It also allows the knowledge to be spread across different European countries: the project facilitates knowledge exchange and teams can grow together, propagating what they have learned in their local institutions and ecosystems.’

‘Coordinating a project of this scale, with projects across different countries, sectors and areas of expertise, is inherently challenging,’ adds Vanessa Iglesias. ‘However, the DARE consortium involves partners who have worked together on previous projects, which facilitates communication and cooperation.Moreover, governance structures were put in place from the outset, including clear work packages for management and communication. It is also worth mentioning that BSC has extensive experience coordinating projects with large consortia, with a well-qualified, experienced team.’

The ambition to create made-in-Europe technology and build a successful chip industry also poses the question of how open the research should be: is sharing research and roadmaps openly the way forward, or should Europe start guarding its intellectual property (IP) more closely? ‘Commercialization in DARE is being driven by the three chiplet owner companies, while the startups and small / medium enterprises will develop their own IPs for future phases,’ says Osman.

‘We take the European Commission’s mantra “as open as possible, as closed as necessary” as our starting point. From the early stages of the project, knowledge and IP issues will be managed by the innovation managers, who will identify and monitor, as early as possible, results that have the potential to be exploited and who will support their owners to define strategies to protect and make concrete use of these results,’ adds Vanessa. ‘DARE will follow two approaches: one that is primarily industry-oriented, with a strong focus on commercialization, and the other taking a more exploratory path, embracing higher-risk research and innovation.’

Osman Ünsal presenting DARE at the EuroHPC JU booth at ISC-HPC

DARE’s legacy

What kind of impact will DARE have in the long run? The main goal is for Europe to shift from being a consumer to a producer of HPC / AI technology, according to Osman. ‘In 10 years’ time, I’d like to see a RISC-V system based on European technology among the top three or four players in the top 500 lists – whether HPC or AI,’ he says.

Yet the collaboration between European partners is also a key part of this effort. ‘Beyond the concrete results, I would like DARE to prove the success of a federated approach to building European technology, demonstrating how bringing universities, research centres and industry players can work together to achieve our technical sovereignty.’

Along the way, the project will build much-needed capacity in European design-to-fab expertise, verification skills, and in-depth knowledge of state-of-the-art architectures, building on work started in EPI.