Per Stenström

Per Stenström earned his PhD degree in computer engineering in 1990 from Lund University, Sweden. Since 1995 he is a Professor of Computer Engineering at Chalmers University of Technology, Sweden. His research interests are devoted to high-performance computer architecture and he has made major contributions to especially high-performance memory systems. He has authored or co-authored four textbooks and more than 150 publications in international journals and conferences and more than ten patents. He is regularly serving program committees of major conferences in the computer architecture field and is currently an Associate Editor-in-Chief of the Journal of Parallel and Distributed Computing, Senior Associate Editor of ACM Transactions on Architecture and Code Optimization, Topical, Associate Editor of IEEE Transactions on Computers and IEEE Micro. He has served IEEE Transactions on Parallel and Distributed Processing, the IEEE TCCA Computer Architecture Letters, and others. He co-founded the HiPEAC Network of Excellence funded by the European Commission. He has also acted as General and Program Chair for a large number of conferences including the ACM/IEEE Int. Symposium on Computer Architecture, the IEEE High-Performance Computer Architecture Symposium, the IEEE International Parallel and Distributed Processing Symposium and the ACM International Conference on Supercomputing and IEEE/ACM PACT. He has been part of more than ten European projects and is currently coordinating H2020 EuroLab4HPC. He is a Fellow of the ACM and Fellow of the IEEE and a member of Academia Europaea, the Royal Swedish Academy of Engineering Sciences, the Spanish Royal Academy of Engineering and The Royal Society of Arts and Sciences in Gothenburg.