Jaume Abella

Jaume Abella is a senior PhD. Researcher in the CAOS group at BSC and member of HIPEAC. His research focuses on the timing and functional validation and verification of safety-related real-time systems, performance analysis, reliability analysis and hardware/software co-design. He worked at the Intel Barcelona Research Center from 2005 to 2009 in the low-level design and modelling of circuits and microarchitectures for fault-tolerance and low power, and led the group on memory hierarchies. Jaume authored 15 patents at Intel. He joined the BSC in 2009 where he is/has been in charge of hardware designs for FP7 PROARTIS, the hardware work-package in FP7 PROXIMA, BSC certification activities in ARTEMIS VeTeSS and H2020 SAFURE BSC contribution. Jaume is/has been also involved in four ESA projects. He has authored more than 100 papers in top conferences and journals in the area. He is co-advisor of ten PhD and Master students.