Daniel J. Sorin is a Professor and Associate Chair for Education in the Department of Electrical and Computer Engineering and a Professor of Computer Science at Duke University, where he has been on the faculty since 2002. He received a PhD and MS in electrical and computer engineering from the University of Wisconsin, and he received a BSE in electrical engineering from Duke University. He is the recipient of an NSF Career Award and two teaching awards at Duke. His research interests are in computer architecture, with a focus on fault tolerance, verification, and memory system design.
He is the author of “Fault Tolerant Computer Architecture” and a co-author of “A Primer on Memory Consistency and Cache Coherence.” He was the editor-in-chief of IEEE Computer Architecture Letters and the Program Chair of ISCA 2025.