According to the announcement, TC2 incorporates a dual-core architecture with three levels of on-chip cache memory and a vector processing unit compatible with the RISC-V Vector 1.0 (RVV 1.0) extension, featuring eight vector lanes equipped with four floating-point units (FPUs) each. The design has been optimized for Intel 18A technology and reaches a target frequency of 1.5 GHz.
During this new phase, the BZL team will carry out the first experimental tests of the chip using the validation boards prepared for the TC2. These tests will make it possible to verify the correct functioning of the processor’s various blocks, evaluate its performance, and gather key information for future generations of the Cinco Ranch family.
HiPEAC member Miquel Moretó, the head of hardware at BZL and director of the HPC Architectures Research Area at BSC-CNS, said: ‘The arrival of TC2 turns months of design and validation into a real chip that we can now put to the test. It’s a fundamental step toward our vision of next-generation European RISC-V processors.’