Given that processors are the basis of computing, the ability to produce chips is a key plank of technological sovereignty. The American chip giant Intel was, for many years, the dominant force in consumer chips, but it was blindsided by the emergence of the mobile market, in which IPs developed by the British company Arm gained dominance.
For many years, the European Commission supported the development of Arm-based IP through research projects that helped pave the way for the expansion of the low-power chip architecture into the high-performance computing (HPC) and datacentre sectors. With Arm’s acquisition by Softbank in 2016 and the UK’s exit from the European Union, it became clear that the EU might need to diversify strategies to strengthen its technological autonomy.
Enter RISC-V
The emergence of the open RISC-V instruction set architecture (ISA) in 2010 offered a new possibility: an avenue by which Europe could develop its own technological ecosystem and, in the process, build much-needed hardware experience in the bloc. Early champions of the RISC-V ISA in Europe included ETH Zürich and the University of Bologna, whose joint PULP Platform collaboration started taping out chips in 2013.
This opened up the intriguing possibility that RISC-V could be the basis of future, designed-in-Europe high-performance systems. In fact, thanks to the lack of incumbents, Europe could even become a trailblazer in this area, as Mateo Valero of Barcelona Supercomputing Center (BSC) explained to HiPEAC in 2022 (see HiPEACinfo 66): ‘By expanding the RISC-V ecosystem, Europe can leapfrog into new technology areas and overtake the current leaders.’
In 2018, the European Processor Initiative (EPI) was launched to develop the fundamental European technologies for a high- performance computing node based on European technology, explains Filippo Mantovani, an established researcher at BSC. ‘The European Processor Initiative has two main development strands. The first is the development of a general-purpose processor, based on the Arm architecture, and its natural successor is the EUPEX project. The second strand involves the development of a set of RISC-V-based accelerators, and this strand is being built upon by the EUPILOT and eProcessor projects,’ he notes.
The EPI HPC node comprises an Arm-based central processing unit (CPU), which acts as a host, coupled with RISC-V based accelerators. Within the accelerator strand, known as EPAC, there are three pillars: the VEC, a vector central-processing unit(CPU), is being developed by Barcelona Supercomputing Center and Semidynamics; the VRP (VaRiable Precision) accelerator is being developed by CEA; and the STX (Stencil Processor) accelerator is a joint effort between ETH Zürich and Fraunhofer.
Why RISC-V?
The advantage of RISC-V is that it offers a standard among the various proprietary ISAs on the market today – rather as the USB (universal serial bus) standard means you don’t have to buy a different cable for each device. According to Filippo, the ISA is the most important interface in computing as it regulates how software interacts with hardware. Examples of ISAs include Intel’s X86-64, SPARC (developed at Berkeley), MIPS (developed at Stanford), IBM Power, and Arm.Developed at Berkeley in 2010, the open RISC-V ISA offers several advantages over the proprietary ISAs that have dominated for decades. First, it is open and royalty free, allowing anyone to develop chips based on the RISC-V architecture. This flexibility enables diverse business models where both companies and research entities can adopt RISC-V, deciding independently how to commercialize or protect their final products. Second, having a universal ISA significantly benefits system software. Essential tools, such as compilers, can rely on a robust, shared core that is developed collaboratively and supported by companies with vested interests in the RISC-V ecosystem. Finally, RISC-V is modular, with a base set of core instructions that can be expanded through extensions. These extensions add specialized functionality, tailoring hardware to specific needs. One noteworthy example is the vector extension, ratified in 2021, which has been adopted within EPAC’s VEC to enhance computational capabilities.
Milestones in European processor design
For the VEC, the EPI team opted for a vector architecture, using long vectors. Such architectures can be programmed like standard scalar processors using a standard programming language allowing for portability and eschewing the complexity of the host-device model embraced by NVIDIA, according to Filippo. ‘With NVIDIA’s graphics processing units (GPUs), programming requires a different binary for the accelerator, plus you have the overhead of offloading to the GPU and the overhead of moving data to and from the GPU, all of which makes this model complex for the programmer and less portable among different HPC systems.’RISC-V is a modular ISA, with a mandatory base ISA which can be extended for different applications. The RISC-V Vector (RVV) extension of RISC-V extends this ISA with vector instructions. The EPI project realized the first European RISC-V vector CPU implementing the RVV extension defined by the RISC-V committee which booted Linux and supported a vector unit with very large vectors of 256 double-precision (DP) elements; for comparison, other CPU vendors, such as Intel, used a maximum vector length of eight DP elements. ‘The project gave us the opportunity to explore this design point in comparison with other RISC-V architectures, CPUs, GPUs and other long-vector architectures such as the NEC Aurora SX. In other words, it allowed us to experiment with a design point that is somewhat outside the mainstream and companies would be wary of exploring,’ says Filippo.
Bringing up the EPAC (chip on the right)Drawing on lessons learned in the EU-funded Mont-Blanc project, which helped expand the Arm ecosystem for HPC applications, the EPI has recognized the need to solidify the RISC-V software base to contribute to a solid HPC software stack. Compilation and system software are a key area of focus, with one highlight being the support for the RISC-V vector extension v1.0 in the LLVM compilation infrastructure.
More generally, the EPI and the other EU projects adopting RISC-V have provided European teams with the experience of validating a full technological chain needed to produce a chip, allowing them to gain expertise in which Europe was severely lacking. ‘The EPI has produced European IPs which have been validated through the tapeout process,’ says Filippo. ‘In addition to building capacity in processor design in Europe, it also produced physical chips, which act as an inspiration for others considering this path.’
This work also helped nurture an environment of ‘development driven by measurement’, Filippo notes, breaking the traditional ‘hardware vs. software’ conflict. ‘Thanks to the open standard, having access to the architectural internals, and having the tools to inspect them, allows us to measure and understand in depth the effect of design points, so we can then report back to hardware engineers, compiler developers and even scientists who are early adopters of our systems,’ he says. Filippo notes that GPUs, for example, while powerful, are also far from fully exploited, which means that the computational efficiency of many supercomputers tends to be low. While there will always be a compromise between specialized hardware and the software that can exploit it, close cooperation between hardware designers and software developers helps deliver a more efficient product.
To ensure its applicability in real-life settings, the technology developed as part of EPI is also being tested on real scientific codes with the European Centres of Excellence and other scientific communities. These include:
- CEEC, which focuses on computational fluid dynamics (CFD), and which has tested Alya, Flexi, Neko, NekRS, WaLBerla, and SOD2D codes on EPI technology;
- Plasma-PEPSC, which focuses on plasma physics simula- tions and which has tested the BIT1, GENE, GENE-X, PIConGPU, and Vlasiator codes;
- ChEESE, which developed exascale-ready solid earth simulation codes and will test the codes ExaHyPE, Salvus, SPECFEM3D, HySEA, SeisSol, AWP-ODC, FALL3D, ASHEE;
- and MultiXscale, which promotes the award-winning EESSI code for multiscale simulations.
The future of RISC-V-based HPC in Europe
The near future will see the tapeout of the VEC and its integration into boards as part of EUPILOT. This will be followed by a project to develop large-scale European HPC and artificial intelligence (AI) technologies based on RISC-V.
Could future RISC-V based accelerators challenge the dominance of GPUs in the HPC market? While Filippo acknowledges that competing with NVIDIA is far-fetched, he believes they could attract profiles of research institutions and companies that care about efficiency. ‘However, the development of this technology is a long process, as our experience with Arm-based processors for HPC at BSC has shown. In 2011, for the Mont-Blanc project, we started experimenting with Arm chips using Android development kits for HPC installations. It took another 10 years for the Arm-based supercomputer Fugaku to see the light – and that was with Arm and Fujitsu driving this work in the background. It’s easy to see how widespread adoption of RISC-V accelerators for HPC could take even longer,’ he adds.
The RISC-V panel at HiPEAC 2023 in Toulouse