For the 2023 edition of the awards, five candidates were selected, as detailed below:
- Behzad Salami, Barcelona Supercomputing Center (BSC): FPGA-Shell: Rapid Emulation of RISC-V Designs on FPGAs
- Christos Strydis, Erasmus Medical Center and Delft University of Technology: Enhancing Pavlovian-training experiments with GPU-accelerated machine learning
- Salvador Trujillo, ORBIK Cybersecurity: ORBIK Cybersecurity: A cybersecurity spinoff for equipment manufacturers
- Lennart M. Reimann, Niko Zurstraßen, Jose Cubero, Lorenzo Pfeifer, Jan Moritz Joseph RWTH Aachen: Empowering next-generation processor design: EDA tools for faster time-to-market
- Jorge Fernandez-Berni, Institute of Microelectronics of Seville (CSIC-Universidad de Sevilla): BiodAIverse: Smart conservation technologies
Further information
Behzad Salami, Barcelona Supercomputing Center (BSC): FPGA-Shell: Rapid Emulation of RISC-V Designs on FPGAs
Emulating chip designs using field-programmable gate arrays (FPGAs) is a crucial step to validate the correctness of register transfer level (RTL) design before undertaking an expensive fabrication process. With the open-source RISC-V instruction set architecture (ISA) democratizing processor design, rapid FPGA validation is gaining even greater significance. However, FPGA emulation can itself be a bottleneck, as it requires thorough understanding of the underlying hardware and different tools and skills to processor design.
Developed by BSC during the EuroHPC project MEEP, FPGA-Shell streamlines the pre-silicon validation of RISC-V custom processors on FPGAs by automating the emulation process. FPGA-Shell automatically creates and compiles the FPGA project by connecting the RTL RISC-V design to commonly used FPGA peripherals, simply by editing a configuration file. Finally, the framework builds the project and creates the FPGA bitstream automatically, all with minimal human intervention and without the need for in-depth FPGA knowledge.
FPGA-Shell has been integrated with several open-source RISC-V systems as well as custom RISC-V designs at BSC. In collaborations with academia and industry, it is constantly evolving with new features. For example, as a part of recent agreement with Lenovo, FPGA-Shell will be supported financially and technically for the emulation of multi-core RISC-V designs partitioned onto multiple FPGAs. The FPGA-Shell source code is also publicly available on GitHub for further developments.
Christos Strydis, Erasmus Medical Centerand Delft University of Technology: Enhancing Pavlovian-training experiments with GPU-accelerated machine learning
In neuroscience, Pavlovian eyeblink conditioning is a crucial experiment for assessing human learning processes. Traditionally, researchers have tracked eyelid movements using potentiometers or electromyography. Recently, computer vision and image processing have offered alternatives, but these require human involvement and lack real-time capabilities.
To address this, the NeuroComputing Laboratory of the neuroscience department at the Erasmus Medical Center in Rotterdam joined forces with the startup BlinkLab, which turns mobile phones into devices for conducting neurobehavioural evaluations. Researchers evaluated face- and landmark-detection algorithms for automated eyelid tracking, a technique which could help enable closed-loop experiments with promise for insights into neurological disorders.
After evaluating various detection algorithms, the histogram-of-oriented-gradients (HOG) and the ensemble-of-regression-trees (ERT) algorithms were chosen for eyelid detection and accelerated on graphics-processing units (GPUs), yielding substantial speed improvements. The algorithm achieved an application performance of more than 1,875 frames per second (FPS), surpassing real-time requirements for human eyeblink conditioning.
Salvador Trujillo, ORBIK Cybersecurity: ORBIK Cybersecurity: A cybersecurity spinoff for equipment manufacturers
As embedded systems become increasingly interconnected, they are also increasingly susceptible to vulnerabilities. In addition, they are increasingly subject to regulatory requirements, such as the European Union’s Cyber Resilience Act, as well as needing to meet customer requirements. Over the last few years, IKERLAN has developed a range of technological assets aimed at enhancing the cybersecurity of equipment manufacturers, with a particular emphasis on those incorporating industrial control systems with dedicated embedded electronics.
Drawing on IKERLAN’s expertise and resources, the ORBIK Cybersecurity spinoff was created to provide cybersecurity-assessment services and help clients meet industry standards, such as IEC62443. The fledgling company is already working with clients including in the energy sector, such as equipment providers for power grids.
Find out more about ORBIK Cybersecurity in this corporate video.
Lennart M. Reimann, Niko Zurstraßen, Jose Cubero, Lorenzo Pfeifer, Jan Moritz Joseph , RWTH Aachen: Empowering next-generation processor design: EDA tools for faster time-to-market
In recent years, processor complexity has been growing exponentially, and design tools have been unable to keep pace. Current electronic design automation (EDA) tools are often unable to fully leverage higher core counts in contemporary processors, thus achieving only marginal performance gains, while having to cope with larger, increasingly complicated designs.
In this technology transfer, the team at RWTH Aachen developed two design tools and transferred these to a major international information and communication (ICT) company as part of joint research projects. The first, a tool for rapid prototyping using abstract modelling of the target hardware, allows users to understand application requirements and derive an initial architecture. The second, a parallel simulation kernel for the open-source project gem5, enables microarchitecture optimization and provides an understanding of the system-level performance impact of low-level design decisions. These tools are being deployed at scale for the company’s next generation of processors.
Jorge Fernandez-Berni, Institute of Microelectronics of Seville (CSIC-Universidad de Sevilla): BiodAIverse: Smart conservation technologies
Quite apart from the incalculable loss to the planet, the sixth mass extinction which is currently ongoing also constitutes a critical threat to the future of human civilization due to the associated degradation of ecosystem services. Technology can play a role in helping to bend the curve of mass extinctions by keeping a record of the state of species and ecosystems, identifying causes of extinction and degradation, assessing the effectiveness of mitigation measures, and monitoring the evolution of the environment while collecting data to drive future actions and make informed decisions.
The spinoff BiodAlverse came about from many years of interdisciplinary research on conservation technologies jointly conducted by two groups at the Institute of Microelectronics of Seville and Doñana Biological Station in Andalusia, Spain. Leveraging researchers’ extensive know-how in embedded artificial intelligence (Al) and internet-of-things (loT) systems, as well as in the application of technology to conservation, BiodAlverse provides a scalable, end-to-end technological infrastructure for effective wildlife monitoring, ranging from real-time reporting to long-term habitat assessment.
The key technologies at the core of BiodAlverse’s value proposition are:
- a modular, multi-sensor, low-cost, low-power, internet-of-things (loT) platform that can be easily adapted to different customer requirements;
- artificial intelligence (Al) algorithms tailored for efficient execution on embedded systems; and
- a cloud platform that collects data coming from systems deployed in the field and aggregates them for proper visualization and analysis through customized panels and notifications.
Further information on BiodAIverse may be found in the ‘SME snapshot’ article in HiPEACinfo 69 (July 2023).