In the 2022 edition, six candidates have won an award, as detailed below.
- Georgios Keramidas, Aristotle University of Thessaloniki: Design space exploration methodology for tensor train decomposition
- Yun Zhou, Ghent University: RWRoute: Open-source, timing-driven routing for commercial FPGAs
- Said Hamdioui, Delft University of Technology: Device-aware testing: The road towards one defective part per billion
- Valerio Schiavoni, University of Neuchâtel: Full-stack trusted WebAssembly runtime using Intel SGX enclaves for secure crypto-currency credit scoring
- Nuno P. Lopes, Instituto Superior Tecnico (IST), ULisboa : Alive2: Automatic Verification of LLVM Optimizations
- Petar Radojković, Barcelona Supercomputing Center: IO(n) Key-value Sort with Processing in Memory
Further information
Georgios Keramidis, Aristotle University of Thessaloniki: Design space exploration methodology for tensor train decomposition
The THESSIS group at Aristotle University of Thessaloniki and the University of Plymouth (Professor Vasilios Kelefouras) developed a design space exploration (DSE) methodology for employing low-rank factorization (LSF), a well-known compression technique, in the dense layers of a deep neural network (DNN). The DSE methodology drastically prunes the huge LSF design space. The technology has been transferred to Think Silicon, a provider of ultra-low-power graphics processing units (GPUs) and machine learning accelerators.
Yun Zhou, Ghent University: RWRoute: Open-source, timing-driven routing for commercial FPGAs
The Hardware and Embedded Systems (HES) research group at Ghent University has been investigating how to reduce routing runtime for field-programmable gate arrays (FPGAs) and thereby achieve a shorter FPGA design cycle, which would improve designer productivity. Building on previous work, together with Xilinx (now the AMD Adaptive & Embedded Computing Group), the group developed RWRoute, an open-source, timing-driven router for commercial FPGAs (FPT 2021). RWRoute has been integrated into the AMD RapidWright framework under the Apache 2.0 licence, laying the groundwork for fast, domain-specific FPGA implementation solutions.
Said Hamdioui, Delft University of Technology: Device-aware testing: The road towards one defective part per billion
The Device‐Aware‐Test (DAT) (patent pending) developed at TU Delft seeks to overcome the shortcomings of existing commercial solutions for outgoing product quality in, for example, memory devices. This solution incorporates the impact of the manufacturing physical defect into the technology parameters of the device and thereafter in its electrical parameters, before integrating the model in a memory fault-analysis simulation platform. Using the insights generated, optimal and appropriate test solutions are developed. Working with industrial partners including imec demonstrated the advantages of DAT, which has won several best paper awards.
Valerio Schiavoni, University of Neuchâtel: Full-stack trusted WebAssembly runtime using Intel SGX enclaves for secure crypto-currency credit scoring
As part of the EU-funded project VEDLIoT, the team at the University of Neuchatel (UniNE) contributed novel libraries and support to deploy WebAssembly applications inside trusted execution environments (such as Intel SGX, or ARM TrustZone). Credora (formerly X-Margin Inc.) collaborated with UniNE to help develop and use these novel libraries in their distributed architecture and technology to power their provably private credit evaluations that promote transparent crypto credit markets. Several of the enhancements to the WebAssembly runtime and libraries have been merged into open-source repositories, further transferring the results towards widespread public use.
Nuno P. Lopes, Instituto Superior Tecnico (IST), ULisboa : Alive2: Automatic Verification of LLVM Optimizations
Alive2 is an automatic compiler verification tool that uses translation validation to automatically verify optimizations of the LLVM compiler without requiring any change in LLVM or any change in the developers’ workflow. It has been integrated into LLVM, developed as part of joint research with Azul and Google, and used by AMD, Apple, Microsoft and Sony PlayStation, among others.
Petar Radojković, Barcelona Supercomputing Center: O(n) Key-value Sort with Processing in Memory
In the context of the bilateral sponsored research agreement, BSC provided dedicated services to Micron Technology, Inc. (Micron) to design and evaluate processing-in-memory architectures for high-performance computing. BSC provided its expertise in HPC applications, programming models, system simulation and performance analysis to evaluate the potential benefits of processing-in-memory architectures capable of doing key-value sort directly in the DRAM. Through modest enhancements to DRAM, the team exploited the parallelism inherently available in memory devices to enable sort, leading to significant performance improvements.
Congratulations to all!