The slowing of Moore’s Law and the escalating costs of monolithic chip manufacturing have positioned chiplet-based architectures as the dominant paradigm for future systems. A chiplet-based architecture consists of the modular integration of multiple System-on-Chip (SoC) dies to improve computing performance, integration density, and memory capacity while maximizing silicon utilization by leveraging heterogeneous semiconductor process technologies. It is based on the assembly of specialized functional components – including CPU and GPU cores, memory modules, and domain-specific accelerators – within a unified system. This modular paradigm enables the efficient design of increasingly complex architectures through the composition of reusable and independently optimized building blocks. This design approach offers unprecedented flexibility, scalability, and cost-effectiveness. The heterogeneous integration enabled by chiplets further allows designers to combine the most suitable process technologies for each function—for instance, using advanced nodes for compute chiplets while relying on more mature, cost-effective nodes for I/O and memory functions.
However, this modularity comes at the cost of an explosion in design complexity: the design space now encompasses not only traditional core-level and memory hierarchy parameters but also chiplet composition, inter-chiplet communication fabrics, packaging technologies (2.5D interposers, bridges, 3D stacking), and thermal management strategies. Furthermore, system integrators must consider the diverse characteristics of chiplets from multiple vendors, each with different performance, power, area, and reliability profiles. This multidimensional design space renders traditional exploration approaches computationally intractable.
Existing DSE methodologies exhibit several critical limitations when applied to chiplet-based systems. Traditional cycle-accurate simulation is infeasible for large-scale multi-chiplet systems due to host-machine performance and memory limitations. There is no unified framework that integrates the diverse tools needed for chiplet-level, inter-chiplet, and package-level evaluation. Designers must manually navigate between architectural simulators, thermal models, communication network simulators, and packaging analysis tools, leading potential inconsistencies in evaluation. Most approaches focus on one or two objectives (typically performance and power), neglecting area, cost, thermal, and real-tima and aging metrics. Few frameworks support the co-exploration of architecture, mapping, and packaging decisions in an integrated manner. Design choices—such as which chiplets to include, how to distribute workload across them, and how to package them—are deeply interdependent, yet existing approaches often treat them sequentially or in isolation.
This thesis proposes novel approaches for Design Space Exploration to address the unique challenges of chiplet-based system design. The research will propose a DSE methodology that combines multifidelity simulation tools, analytical models, and advanced multi-objective optimization algorithms to explore the vast design space of chiplet-based architectures. To achieve that, it establishes a formal modelling framework to capture hierarchical interdependencies across core, chiplet, inter-chiplet design parameters. Second, it develops a multi-fidelity evaluation strategy integrating heterogeneous simulation tools—combining fast virtual prototyping with detailed models (thermal, power, communication, and timing)—for fast yet accurate early-stage exploration. Third, it adapts multi-objective optimization algorithms, including genetic algorithms and reinforcement learning, to navigate the vast heterogeneous design space, with novel techniques tailored to the hierarchical nature of chiplet design. The framework will be validated on representative workloads, demonstrating significant improvements in power, performance, area, but also thermal, aging and real-time metrics compared to state-of-the-art approaches.
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