RISC-V is an open-source instruction set architecture (ISA) for computer processors. It is designed to be simple, modular, and extensible, with a minimalist approach to instruction set design that aims to provide flexibility, performance, and energy efficiency. RISC-V was developed at the University of California, Berkeley in 2010 and has since gained popularity as a free and open alternative to proprietary ISAs like ARM and x86. The openness of RISC-V allows different chip manufacturers to implement their architectures on top of the same ISA.
This course provides an introduction to RISC-V and vector supercomputing. The lectures cover the basics of RISC-V architecture. A particular focus will be given to the RISC-V vector extensions (RVV) and especially to an implementation using large vectors. Students will learn how RVV compares to other vector architectures and explore a design point leveraging up to 16-kb-wide vectors.
Students will experience the tools and libraries available for vectorization and the challenges and limitations of the process. A prototype platform implementing a European RISC-V CPU supporting the RVV extension will be presented and used for test and analyzing simple codes and parallel scientific applications. By the end of this course, students will have a deep understanding of RISC-V and vector architectures, as well as methods and tools to analyze the performance of codes running on them.