The vast majority of today’s computer processors are multicore processors that implement cache coherent shared memory. In these systems, the definition of memory system correctness is the memory consistency model (MCM), which specifies the legal orderings of reads and writes across the multiple threads of a process, as well as whether the writes appear atomic. The MCM is a fundamental part of a computer architecture that must be fully understood by both architects and compiler writers. Many MCMs exist, and they differ in what ordering and atomicity guarantees they provide. For example, Sequential Consistency (SC) guarantees a total order of all reads and writes that respects program order at every thread. The MCM is architecturally visible to software as an abstraction, and considerable work has sought to achieve as much performance as possible while providing a given MCM. As part of providing a given MCM, most multicore processors implement a cache coherence protocol that ensures that each block of memory, at any given time, can either be read and written by one core or read by zero or more cores. There are many different ways to implement cache coherence protocols, trading off performance, complexity, and storage overhead for metadata.
This course will cover the fundamentals of memory consistency and cache coherence that every architect and compiler writer should know, as well as provide pointers to advanced topics, open areas of research, and current debates in the field.