In this course, we will delve into the RISC-V open-source instruction set architecture (ISA) as a means to design domain-specific yet programmable edge AI systems, from IoT-class solutions to more powerful edge accelerators.
After an introduction to the RISC-V ISA and its main characteristics, we will explore how ISA customization and low-power microarchitectural design can enable low-area-cost processors for edge AI. We will then analyse their integration into low-power multi-core MIMD compute clusters, and architectural solutions that can reduce fetch-stage power consumption to achieve accelerator-like energy efficiency.
We will also analyse the von Neumann bottlenecks and scalability issues of this approach and investigate architectural solutions to address them. We will cover heterogeneous RISC-V compute clusters integrating programmable processors and tightly coupled accelerators, as well as alternative RISC-V streaming processors and specialized vector compute clusters. For these approaches, we will discuss the main architectural trade-offs through state-of-the-art examples from the literature, with a brief outlook on in-memory computing and many-core scalability.
Overall, the course aims to provide participants with cutting-edge knowledge of hardware/software co-design solutions based on the RISC-V ISA for building highly energy-efficient edge AI processors for area- and power-constrained devices.