Giuliano Sisto

Giuliano Sisto received his M.Sc. from Politecnico di Bari in 2018. He obtained a Ph.D. degree from the Universite’ Libre de Bruxelles (ULB), in collaboration with imec and Cadence Design Systems, in 2022. In November 2021 he joined imec as full-time researcher. Since September 2023 he works as chiplet architect in the imec compute and system architecture group. His research interests include system architecture and technology co-optimization using emerging technologies and packaging.