- Graph of Thoughts: Solving elaborate problems with large language models – Maciej Besta, ETH Zürich, Switzerland, Germany
- Roofline AI – Jan Moritz Joseph, Roofline GmbH, Germany
- GenoGra: Pangenomic analysis platform – Marco Santambrogio, Politecnico di Milano, Italy
- FAiNDER: FAiND the best hardware for your Al application – Petar Radojković, Barcelona Supercomputing Center, Spain
- Interconnection network and memory subsystem IPs for high-performance, scalable SoC solutions – Madhavan Manivannan, InfiniNode Technologies AB, Sweden
- LinguaFranca: A language to bring intelligent systems to life – Jeronimo Castrillon and Christian Menard, TU Dresden, Germany
- BlueSign: Translating Italian Sign Language into avatar signs – Roberto Giorgi University of Siena, Italy
- From DaCe to Daisytuner: Performance optimization as a service – Lukas Trümper Daisytuner, Switzerland
The winners
Graph of Thoughts: Solving elaborate problems with large language models
Maciej Besta, ETH Zürich, Switzerland
Graph of Thoughts (GoT) is an advanced framework that enhances large language models (LLMs) like GPT, PaLM, and LLaMA by allowing their reasoning to form a flexible graph structure, surpassing prior methods such as chain-of-thought and tree-of-thought. This approach enables more sophisticated problem-solving by modelling thoughts as vertices and their dependencies as edges, mimicking human cognitive processes. GoT has shown up to 62% improvement in tasks like sorting and document merging while reducing costs by 31%, supported by a strong GitHub presence with over 2,100 stars.
Industry applications include aiding a major chemical producer in scalable data analytics, enhancing event detection for a rare disease treatment leader, and aiding in semantic content indexing and legal compliance monitoring for media broadcasters, highlighting the scalability and robustness of the framework across sectors.
Roofline AI
Jan Moritz Joseph, Roofline GmbH, GermanyRooflineAI GmbH aims to make artificial intelligence (AI) deployment at the edge flexible, efficient and easy. The foundation of Roofline’s development was established at RWTH Aachen University, where Roofline was spun off and successfully completed an IP transfer. Now, Roofline offers an innovative deployment solution as a software development kit (SDK) that utilizes a retargetable AI compiler toolchain.
GenoGra: Pangenomic analysis platform
Marco Santambrogio, Politecnico di Milano, ItalyPan-genomics is a novel approach to analysing genomic data. Instead of a single reference genome, it involves the usage of a composite reference of multiple genomes sampled from across a wider range of variability within a species. However, while pan-genomics ensures maximum accuracy and simplicity, it is computationally demanding and slow.
To overcome this problem, the ‘GenoGra - Genome Analysis, Unleashed’ research project was born in 2020 at the NECSTLab at Politecnico di Milano, aiming at developing high-performance solutions for pan-genomic analysis. The project’s main outcome was a methodology to accelerate the sequence-to-graph alignment process on heterogeneous computing systems equipped with graphics processing units (GPUs), protected by an Italian patent application (2022) and its PCT extension (2023).
In June 2023, the research team founded GenoGra s.r.l., an innovative Italian startup that aims to bring the outcomes of the research project to the market. To achieve its goal, the company is developing a user-friendly platform where bioinformaticians can effortlessly run accurate pan-genomic tools that ensure high performance, thanks to the patented technology.
FAiNDER: FAiND the best hardware for your Al application
Petar Radojković, Barcelona Supercomputing Center, Spain
Team: Mariana Carmin, Javier Beiro, Victor Xirau, Pouya Esmaili, Petar Radojkovic, Eduard Ayguadé (all BSC), Emanuele Confalonieri, Rishabh Dubey and Jason Adlard (all Micron, United States)
In the context of a bilateral sponsored research agreement with Micron Technology, Inc., Barcelona Supercomputing Center (BSC) developed the FAiNDER online platform, which is designed to transform how researchers and developers navigate the rapidly evolving AI landscape. The platform is designed to help researchers and developers to explore and enhance the most relevant AI models and their performance.
The FAiNDER offers an up-to-date, comprehensive, filterable tables and interactive charts, making it easier to analyse vast amounts of information. It covers all major AI models: deep neural networks, convolutional neural networks, deep learning recommendation systems, transformers, graph neural network and recurrent neural networks. The FAiNDER analysis provides detailed information on all phases of the AI software pipeline, their main architecture, arithmetic operations, data types, memory footprint and the target hardware platforms. It provides reliable information collected from the relevant scientific publications.
Interconnection network and memory subsystem IPs for high-performance, scalable SoC solutions
Madhavan Manivannan, InfiniNode Technologies AB, SwedenRISC-V is rapidly gaining adoption due to its customizability, openness and its potential to drive innovation in future computing systems. As RISC-V–based microprocessors scale to meet the demands of AI and high-performance computing (HPC) applications, the performance of the memory subsystem and network-on-chip (NoC) becomes crucial. To support this scaling, careful optimization of the memory subsystem — especially the last-level cache — and the NoC is essential.
A team of researchers from Chalmers University of Technology recognized that existing interconnect and caching solutions targeting RISC-V do not scale effectively for manycore processors. To address this issue, the team embarked on developing a set of intellectual property (IP) blocks as part of several national and EU-funded projects, including the European Processor Initiative. These IPs include a scalable coherent home node, a high-performance network-on-chip, and an optimized last-level cache.
The team, composed of researchers and faculty from the computer architecture group at Chalmers University of Technology, is set to receive support from Chalmers Ventures, the venture-building arm of the university. Additionally, the team has formed a start-up company, InfiniNode Technologies, aimed at development and commercialization of these technologies and will be led by an experienced business developer. InfiniNode Technologies will collaborate with key academic and industrial partners through various national and European programs to develop the IPs and bring them to market. The company plans to engage with the broader RISC-V community, offering these IP blocks to accelerate the development of next-generation RISC-V-based high-performance system-on-chip (SoC) solutions.
LinguaFranca: A language to bring intelligent systems to life
Jeronimo Castrillon and Christian Menard, TU Dresden, GermanyTeam: Christian Menard, Jeronimo Castrillon (both TU Dresden), Marten Lohstroh, Edward A. Lee (both UC Berkeley ) and Jeff C. Jensen (Xronos Inc.)
Society and industry increasingly rely on software-defined intelligent systems that interact with the physical world. These systems are programmed using mainstream programming models and software frameworks that lack abstractions to guide how software components synchronize, react to inputs, and manifest physical behaviour. As a consequence, such systems rarely provide safety guarantees and suffer from concurrency bugs that are hard to track and can be extremely costly if left unchecked.
Lingua Franca (LF), a large collaborative project originated at UC Berkeley, addresses this challenge with a concurrent programming model with explicit semantics for physical time. LF can run on embedded microcontrollers, multicore systems, and cloud systems, offering the same programming experience across these different tiers of computing platforms, automatically exploiting available parallelism, and delivering deterministic behaviour.
In January 2024, the team at TU Dresden (Christian Menard and Jeronimo Castrillon) together with researchers at UC Berkeley (Marten Lohstroh and Edward A. Lee) and Jeff C. Jensen (ex-Blackrock Neurotech, ex-Creator) co-founded Xronos Inc. to commercialize the LF technology, with the goal of accelerating the pace of innovation in robotics and automation—enabling the creation of intelligent systems we can depend on.
BlueSign: Translating Italian Sign Language into avatar signs
Roberto Giorgi, University of Siena, Italy
According to the World Health Organization (WHO), more than 1.5 billion people (nearly 20% of the global population) live with hearing loss, with 430 million of these having disabling hearing loss. Most of these individuals, particularly those who are prelingually deaf, rely on sign language for communication.
Sign language is crucial for deaf individuals to access most of the information needed for daily life, making it indispensable for their full social integration. For deaf people, sign language is often the first language learned and the preferred way of communication. Sign language is recognized by law in many nations worldwide and should be present in many formal contexts; however, human translators are not enough.
The Computer Architecture Laboratory at the University of Siena, Italy, developed a special encoding technique to integrate Italian Sign Language (LIS) into a larger number of devices. Recent developments involved collaborating with Quest-It, an Italian company specializing in AI solutions, to create an artificial human (displayed as an avatar) able to produce LIS on a web page, making it available in many contexts.
From DaCe to Daisytuner: Performance optimization as a service
Lukas Trümper Daisytuner, SwitzerlandCompilers are essential to software development, converting high-level code into low-level instructions that processors can execute. This process ensures that applications are optimized to leverage a processor’s specific features. However, the optimization techniques employed by modern compilers rely on peephole algorithms and static cost models embedded within the compiler’s code.
The Data-Centric Programming (DaCe) framework, conceived by SPCL a decade ago, shifts the focus towards optimizing dataflow, which has become increasingly critical as the gap between memory speed and computation widens. By explicitly representing programs as dataflow and control-flow graphs with symbolic memory accesses, DaCe enables sophisticated analyses and performance optimizations via metaprogramming. This facilitates the development of efficient software across heterogeneous computing systems.
Building on this foundation, Daisytuner introduces DOCC, a novel framework for automatic performance optimization with an extensible database of performance optimizations, which can be automatically queried by the compiler. Utilizing neural networks, the compiler generates code embeddings for specific code regions and identifies optimal transformations in the database.
DOCC allows developers to:
- Optimize and transpile applications seamlessly across processor architectures, all within the integrated development environment (IDE) of the developers.
- Integrate with compilers via plugins, enabling fully automated performance improvements in autopilot mode.
Thanks to Daisytuner, developers can harness automatic, real-time optimizations without the need for specialized in-house resources, allowing them to meet the increasing performance demands of many applications.
