How did you get into computer architecture research?
Discovering computer science in middle school ignited my love for programming. Growing up, my curiosity about how computers work deepened, focusing on their ‘brain’ — the processors. Taking an undergraduate computer architecture class intensified this interest; I was particularly fascinated by fundamental architecture concepts like speculation, prediction, and caching. This experience confirmed my decision to pursue a PhD in computer architecture, and I have not looked back since.
What are the most pressing research topics in the field?
The global datasphere is experiencing unprecedented growth, with the data generated in the next five years expected to surpass the cumulative amount created since the inception of digital storage. Propelled by advanced technologies like artificial intelligence (AI), the internet of things (IoT), 5G, and industry 4.0, this immense influx of data, often left unexamined, poses both challenges and opportunities.
If we could rise to the challenge of processing at least the bulk of the data flood, we can unleash many momentous societal benefits. I would encourage the next generation of computer architects to move to data-centric architectures and leave behind compute-centric designs. There are several compelling paradigms, including in-memory computing and domain specific customization, that can be leveraged to accomplish this.
What are some of the main challenges for in-memory computing?
The key problem in realizing ‘practical’ in-memory computing is building a software ecosystem around it. This is not a unique problem: graphics processing units (GPUs) faced and overcame it by building CUDA programming frameworks and a customized system-software stack. Specifically, for in-memory computing there are several programming models, and our community needs to converge. Another challenge is data staging, i.e. the problem of placing and aligning data. Von Neumann architectures simply solve this problem by moving data from any memory location to registers via loads, and compute units work out of registers. In-memory computing is unique since the memory units are themselves compute units, thus operand data must be placed in the correct memory locations, and be moved around minimally between computing.
On the technology side, exciting opportunities exist in architecting emerging memory devices such as ferroelectric memories, magnetic memories, and new genre of resistive memories.
How is your research applied?
Our prior work repurposes thousands of existing cache memory arrays into massive vector compute units, providing parallelism several orders of magnitude higher than a contemporary GPU. Additionally, it saves energy spent shuffling data between storage and compute units – a significant concern in big-data applications. Caches that compute can be a game changer for AI: they can add accelerator capabilities to general-purpose processors, avoiding the significant die-area cost of a dedicated accelerator like Google’s tensor processing unit (TPU). For example, we showed that compute-enabled caches in Intel Xeon can improve processor efficiency by 629x for convolutional neural networks (CNNs).
Our research also extends into precision health and genome sequencing. Within this domain, certain projects have required a meticulous co-design approach, incorporating wet-lab procedures, computational biology algorithms, and hardware design. The significance of genetic molecular markers cannot be overstated, particularly for surgical decision-making, cancer diagnosis, and clinical trial enrolment. One notable accomplishment of our research is the demonstration of ultrarapid sequencing of brain-tumour tissue in under 40 minutes, encompassing the process of sampling the glioma tissue to reaching a conclusive diagnosis. Typically, this takes several days to weeks for a lab sendout. Our breakthrough has promising implications for advancing surgical procedures for tumour removal and diagnosis.
Why is the HiPEAC conference a good place to share knowledge?
HiPEAC is a cross-disciplinary community with a strong emphasis on emerging hardware paradigms. I’ve observed a significant collaborative push toward open-source hardware within this community, making it an exciting platform to exchange ideas about our latest cross-stack, domain-specific acceleration efforts.