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2006

Alberto D. Pascual-Montano, Pedro Carmona-Saez, Monica Chagoyen, Francisco Tirado, José María Carazo, Roberto D. Pascual-Marqui, bioNMF: a versatile tool for non-negative matrix factorization in biology., BMC Bioinformatics 7: 366 (2006)
Andreas Hansson, Lars Niklasson, Using Segmentation to Control the Retrieval of Data., IJCNN 2006: 1764-1769
Andreas Persson, Lars Bengtsson, Reverse conversion architectures for signed-digit residue number systems., ISCAS 2006
Andrzej Bednarski, Christoph W. Kessler, Optimal Integrated VLIW Code Generation with Integer Linear Programming., Euro-Par 2006: 461-472
Anila Usman, Mikel Luján, Len Freeman, John R. Gurd, Performance Evaluation of Storage Formats for Sparse Matrices in Fortran., HPCC 2006: 160-169
Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Evaluating SoC Network Performance in MPEG-4 Encoder., SiPS 2006: 250-255
Christoph W. Keßler, Andrzej Bednarski, Optimal integrated code generation for VLIW architectures., Concurrency and Computation: Practice and Experience 18(11): 1353-1390 (2006)
Christoph W. Kessler, Peter Fritzson, Mattias V. Eriksson, NestStepModelica - Mathematical Modeling and Bulk-Synchronous Parallel Simulation., PARA 2006: 1006-1015
Dionisios N. Pnevmatikatos, Aggelos Arelakis, , Variable-Length Hashing for Exact Pattern Matching., FPL 2006: 1-6
Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen, Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts., ASAP 2006: 186-190
George A. Constantinides, Word-length optimization for differentiable nonlinear systems., ACM Trans. Design Autom. Electr. Syst. 11(1): 26-43 (2006)
Giovanni Agosta, Stefano Crespi-Reghizzi, P. Palumbo, Martino Sykora, Selective compilation via fast code analysis and bytecode tracing., SAC 2006: 906-911
Heikki Hurskainen, Jari Nurmi, SystemC Model of an Interoperative GPS/Galileo Code Correlator Channel., SiPS 2006: 327-332
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere, Multi-processor system design with ESPAM., CODES+ISSS 2006: 211-216
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere, Efficient Automated Synthesis Programing and Implementation of Multi-Processor Platforms on FPGA Chips., FPL 2006: 1-6
Jérôme Lemaitre, Ed F. Deprettere, FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications., Euro-Par 2006: 1192-1203
Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere, Requirements for Interfacing IP-Components in Re-configurable Platforms., VLSI Signal Processing 43(2-3): 173-184 (2006)
Jonathan A. Clarke, George A. Constantinides, High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic., FPL 2006: 1-2
Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Leong, FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach., FPL 2006: 1-6
Konstantinos Masselos, George A. Constantinides, Qiang Liu, Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm., FPL 2006: 1-6
Lily R. Liang, Shiyong Lu, Xuena Wang, Yi Lu, Vinay Mandal, Dorrelyn Patacsil, Deepak Kumar, FM-test: a fuzzy-set-theory-based approach to differential gene expression data analysis., BMC Bioinformatics 7(S-4): (2006)
Marco Alexandre Cravo Gomes, Gabriel Falcão Paiva Fernandes, João Gonçalves, Vítor Manuel Mendes da Silva, Miguel Falcão, Pedro Faia, , HDL Library of Processing Units for Generic and DVB-S2 LDPC Decoding., SIGMAP 2006: 17-24
Mattias V. Eriksson, Christoph W. Keßler, Mikhail Chalabine, Load balancing of irregular parallel divide-and-conquer algorithms in group-SPMD programming environments., ARCS Workshops 2006: 313-322
Mikhail Chalabine, Christoph W. Keßler, Peter Bunus, Automated Round-trip Software Engineering in Aspect Weaving Systems., ASE 2006: 305-308
Mikhail Chalabine, Christoph W. Kessler, Crosscutting Concerns in Parallelization by Invasive Software Composition and Aspect Weaving., HICSS 2006
P. Bougas, A. Tsirikos, K. Anagnostopoulos, Isidoros Sideris, Kiamal Z. Pekmestzi, , Segmentation based design of serial parallel multipliers., ISCAS 2006
Su-Shin Ang, George A. Constantinides, Dynamic Memory Sub-System for Reconfigurable Platforms., FPL 2006: 1-2
Timo Vogt, Norbert Wehn, A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding., SiPS 2006: 142-147
Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck, Instruction Transfer And Storage Exploration for Low Energy VLIWs., SiPS 2006: 292-297
Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Alastair Reid, Krisztián Flautner, Design and Implementation of Turbo Decoders for Software Defined Radio., SiPS 2006: 22-27
Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser, Real-time systems for multiprocessor architectures., IPDPS 2006
A. de Dios, B. Sahelices, Pablo Ibáñez, Víctor Viñals, José M. Llabería, Speeding-Up Synchronizations in DSM Multiprocessors., Euro-Par 2006: 473-484
A. Jimeno, J. L. Sánchez, H. Mora, J. Mora, J. M. García-Chamizo, FPGA-based tool path computation: an application for shoe last machining on CNC lathes, Computers in Industry , Volume 57 Issue 2, Elsevier Science Publishers B. V., February 2006
A. Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie, Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori., IPDPS 2006
Abbas Bigdeli, Morteza Biglari-Abhari, Zoran Salcic, Yat Tin Lai, A new pipelined systolic array-based architecture for matrix inversion in FPGAS with Kalman filter case study, EURASIP Journal on Applied Signal Processing , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Abid M. Malik, Jim McInnes, Peter van Beek, Optimal Basic Block Instruction Scheduling for Multiple-Issue Processors Using Constraing Programming., ICTAI 2006: 279-287
Adam Betts, Guillem Bernat, Tree-Based WCET Analysis on Instrumentation Point Graphs., ISORC 2006: 558-565
Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson, A universal performance factor for multi-criteria evaluation of multistage interconnection networks., Future Generation Comp. Syst. 22(7): 794-804 (2006)
Ahmad Zmily, Christos Kozyrakis, Simultaneously improving code size performance and energy in embedded processors., DATE 2006: 224-229
Ahmad Zmily, Christos Kozyrakis, Block-aware instruction set architecture., TACO 3(3): 327-357 (2006)
Ahmed Abdel-Hafez, Ali Miri, Luis Orozco-Barbosa, Scalable and fault-tolerant key agreement protocol for dynamic groups., Int. Journal of Network Management 16(3): 185-202 (2006)
Ajay Joshi, Aashish Phansalkar, Lieven Eeckhout, Lizy Kurian John, Measuring Benchmark Similarity Using Inherent Program Characteristics., IEEE Trans. Computers 55(6): 769-782 (2006)
Ajay Joshi, Joshua J. Yi, Robert H. Bell Jr., Lieven Eeckhout, Lizy Kurian John, David J. Lilja, Evaluating the efficacy of statistical simulation for design space exploration., ISPASS 2006: 70-79
Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John, Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks., IISWC 2006: 105-115
Ajay K. Verma, Paolo Ienne, Towards the automatic exploration of arithmetic-circuit architectures., DAC 2006: 445-450
Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha, Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip., ESTImedia 2006: 33-38
Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha, Global Analysis of Resource Arbitration for MPSoC., DSD 2006: 71-78
Alan Fern, Robert Givan, Babak Falsafi, T. N. Vijaykumar, Dynamic feature selection for hardware prediction., Journal of Systems Architecture 52(4): 213-234 (2006)
Alan Mycroft, Andreas Zeller, Compiler Construction 15th International Conference CC 2006 Held as Part of the Joint European Conferences on Theory and Practice of Software ETAPS 2006 Vienna Austria March 30-31 2006 Proceedings, Springer 2006
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung, A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design., FCCM 2006: 275-276
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung, A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design., FPL 2006: 1-6
Albert Cohen, Marc Duranton, Christine Eisenbeis, Claire Pagetti, Florence Plateau, Marc Pouzet, N-synchronous Kahn networks: a relaxed model of synchrony for real-time systems., POPL 2006: 180-193
Albert Cohen, Sébastien Donadio, María Jesús Garzarán, Christoph Armin Herrmann, Oleg Kiselyov, David A. Padua, In search of a program generator to implement generic transformations for high-performance computing., Sci. Comput. Program. 62(1): 25-46 (2006)
Alberto Ros, Manuel E. Acacio, José M. García, An efficient cache design for scalable glueless shared-memory multiprocessors, CF '06: Proceedings of the 3rd conference on Computing frontiers, ACM, May 2006
Alberto Ros, Manuel E. Acacio, José M. García, An efficient cache design for scalable glueless shared-memory multiprocessors., Conf. Computing Frontiers 2006: 321-330
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Scalable Low-Cost QoS Support for Single-chip Switches., ICPADS (1) 2006: 439-446
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Full QoS Support with 2 VCs for Single-chip Switches., NCA 2006: 239-242
Alejandro Martínez, George Apostolopoulos, Francisco José Alfaro, José L. Sánchez, José Duato, QoS Support for Video Transmission in High-Speed Interconnects., HPCC 2006: 631-641
Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, Jose Flich, Francisco J. Quiles, José Duato, Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support., Euro-Par 2006: 884-895
Alessandro Bardine, Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete, Analysis of embedded video coder systems: a system-level approach, MEDEA '05: Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture, ACM, March 2006
Alessandro G. Di Nuovo, Knowledge Base Extraction for Fuzzy Diagnosis of Mental Retardation Level., STAIRS 2006: 50-61
Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, An Hybrid Soft Computing Approach for Automated Computer Design., STAIRS 2006: 84-95
Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania, Fuzzy decision making in embedded system design., CODES+ISSS 2006: 223-228
Alessandro G. Di Nuovo, Vincenzo Catania, Maurizio Palesi, The hybrid genetic fuzzy C-means: a reasoned implementation, FS'06: Proceedings of the 7th WSEAS International Conference on Fuzzy Systems, World Scientific and Engineering Academy and Society (WSEAS), June 2006
Alessandro G. Di Nuovo, Vincenzo Catania, Santo Di Nuovo, Serafino Buono, Evolving Fuzzy C-Means: An intelligent technique for efficient diagnosis of children mental retardation level from databases with missing values., IC-AI 2006: 290-296
Alessio Bechini, François Bodin, Cosimo Antonio Prete, Editorial message for the special track on embedded systems: applications solutions and techniques., SAC 2006: 889-890
Alex Gontmakher, Assaf Schuster, Avi Mendelson, Inthreads: a low granularity parallelization model, SIGARCH Computer Architecture News , Volume 34 Issue 1, ACM, March 2006
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gregory Shklover, Speculative synchronization and thread management for fine granularity threads., HPCA 2006: 278-287
Alexander Gendler, Avi Mendelson, Yitzhak Birk, A PAB-Based Multi-Prefetcher Mechanism., International Journal of Parallel Programming 34(2): 171-188 (2006)
Alexander Mendiburu, José Miguel-Alonso, José Antonio Lozano, Evaluation of Parallel EDAs to Create Chemical Calibration Models., e-Science 2006: 118
Alexander Mendiburu, José Miguel-Alonso, José Antonio Lozano, Implementation and Performance Evaluation of a Parallelization of Estimation of Bayesian Network Algorithms., Parallel Processing Letters 16(1): 133-148 (2006)
Alexander Mendiburu, José Miguel-Alonso, José Antonio Lozano, M. Ostra, C. Ubide, Parallel EDAs to create multivariate calibration models for quantitative chemical applications., J. Parallel Distrib. Comput. 66(8): 1002-1013 (2006)
Alexander Sayenko, Olli Alanen, Juha Karhula, Timo Hämäläinen, Ensuring the QoS requirements in 802.16 scheduling., MSWiM 2006: 108-117
Alexander Sayenko, Olli Alanen, O. Karppinen, Timo Hämäläinen, Analysis and Simulation of the Signaling Protocols for the DiffServ Framework., NEW2AN 2006: 566-579
Alexander Sayenko, Timo Hämäläinen, Jyrki Joutsensalo, Lari Kannisto, Comparison and analysis of the revenue-based adaptive queuing models., Computer Networks 50(8): 1040-1058 (2006)
Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes, Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism., European Test Symposium 2006: 213-218
Alexandros Bartzas, M. Peón, Stylianos Mamagkakis, David Atienza, F. Catthoort, Dimitrios Soudris, M. Mendias, Systematic design flow for dynamic data management in visual texture decoder of MPEG-4., ISCAS 2006
Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis, Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications., DATE 2006: 740-745
Alfredo Remón, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Parallel LU Factorization of Band Matrices on SMP Systems., HPCC 2006: 110-118
Alfredo Remón, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Cholesky Factorization of Band Matrices Using Multithreaded BLAS., PARA 2006: 608-616
Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha, Unlocking concurrency., ACM Queue 4(10): 24-33 (2006)
Alok Garg, Fernando Castro, Michael C. Huang, Daniel Chaver, Luis Piñuel, Manuel Prieto, Substituting associative load queue with simple hash tables in out-of-order microprocessors., ISLPED 2006: 268-273
Amund Kvalbein, Audun Fosselie Hansen, Tarik Cicic, Stein Gjessing, Olav Lysne, Fast IP Network Recovery Using Multiple Routing Configurations., INFOCOM 2006
Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. van Gemund, PAM-SoC: A Toolchain for Predicting MPSoC Performance., Euro-Par 2006: 111-123
Ana Lucia Varbanescu, Maik Nijhuis, Arturo González-Escribano, Henk J. Sips, Herbert Bos, Henri E. Bal, SP@CE - An SP-Based Programming Model for Consumer Electronics Streaming Applications., LCPC 2006: 33-48
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven, Compositional efficient caches for a chip multi-processor., DATE 2006: 345-350
Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven, Static cache partitioning robustness analysis for embedded on-chip multi-processors., Conf. Computing Frontiers 2006: 353-360
Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven, Throughput optimization via cache partitioning for embedded multiprocessors., ICSAMOS 2006: 185-192
Andreas Fidjeland, Wayne Luk, Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming., FPL 2006: 1-6
Andreas Pietzowski, Benjamin Satzger, Wolfgang Trumler, Theo Ungerer, Using Positive and Negative from Immunology for Detection of Anomalies in a Self-Protecting Middleware., GI Jahrestagung (1) 2006: 161-168
Andreas Pietzowski, Benjamin Satzger, Wolfgang Trumler, Theo Ungerer, A Bio-inspired Approach for Self-protecting an Organic Middleware with Artificial Antibodies., IWSOS/EuroNGI 2006: 202-215
Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, An artificial immune system and its integration into an organic middleware for self-protection., GECCO 2006: 129-130
Andreas S. Andreou, Dimitrios G. Vogiatzis, George A. Papadopoulos, Intelligent Classification and Retrieval of Software Components, COMPSAC '06: Proceedings of the 30th Annual International Computer Software and Applications Conference (COMPSAC'06) - Volume 02 , Volume 02, IEEE Computer Society, September 2006
Andres Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie, Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori., IPDPS 2006
Andy D. Pimentel, Cagkan Erbas, Simon Polstra, A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels., IEEE Trans. Computers 55(2): 99-112 (2006)
Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas, On the Calibration of Abstract Performance Models for System-level Design Space Exploration., ICSAMOS 2006: 71-77
Andy D. Pimentel, Stamatis Vassiliadis, Editorial., VLSI Signal Processing 43(2-3): 111 (2006)
Angelo Duarte, Dolores Rexachs, Emilio Luque, Increasing the cluster availability using RADIC., CLUSTER 2006
Angelo Duarte, Dolores Rexachs, Emilio Luque, An Intelligent Management of Fault Tolerance in Cluster Using RADICMPI., PVM/MPI 2006: 150-157
Anthony Discolo, Tim Harris, Simon Marlow, Simon L. Peyton Jones, Satnam Singh, Lock Free Data Structures Using STM in Haskell., FLOPS 2006: 65-80
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset, A Generic Multi-Phase On-Chip Traffic Generation Environment., ASAP 2006: 23-27
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset, Automatic phase detection for stochastic on-chip traffic generation., CODES+ISSS 2006: 88-93
Antonio Núñez, Advances in video coding for hand-held device implementation in networked electronic media., J. Real-Time Image Processing 1(1): 9-23 (2006)
Antonio Robles-Gómez, Eva M. García, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, A Model for the Development of AS Fabric Management Protocols., Euro-Par 2006: 853-863
Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Integrated Verification Approach during ADL-Driven Processor Design., IEEE International Workshop on Rapid System Prototyping 2006: 110-118
Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Automatic ADL-based operand isolation for embedded processors., DATE 2006: 600-605
Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen, Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder., DDECS 2006: 59-64
Ari Kulmala, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen, Scalable MPEG-4 encoder on FPGA multiprocessor SOC, EURASIP Journal on Embedded Systems , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen, Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA., DSD 2006: 83-88
Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen, Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA., FPL 2006: 1-6
Ari Viinikainen, Jani Puttonen, Miska Sulander, Timo Hämäläinen, Timo Ylönen, Henri Suutarinen, Flow-based fast handover for mobile IPv6 environment - implementation and analysis., Computer Communications 29(16): 3051-3065 (2006)
Ariel N. Burton, Paul H. J. Kelly, Performance prediction of paging workloads using lightweight tracing., Future Generation Comp. Syst. 22(7): 784-793 (2006)
Arik Friedman, Assaf Schuster, Ran Wolff, k-Anonymous Decision Tree Induction., PKDD 2006: 151-162
Armando Sánchez-Peña, Pedro P. Carballo, Luz García, Antonio Núñez, VIPACES Verification Interface Primitives for the Development of AXI Compliant Elements and Systems., DSD 2006: 305-312
Arran Derbyshire, Tobias Becker, Wayne Luk, Incremental elaboration for run-time reconfigurable hardware designs., CASES 2006: 93-102
Artemis A. Christopoulou, Eleftherios D. Polychronopoulos, A Dynamic Lock Protocol for Scope-Consistency sDSM Systems, ICPADS '06: Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1 , Volume 1, IEEE Computer Society, July 2006
Arturo González-Escribano, Diego R. Llanos Ferraris, Speculative Parallelization., IEEE Computer 39(12): 126-128 (2006)
Asadollah Shahbahrami, Ben H. H. Juurlink, Demid Borodin, Stamatis Vassiliadis, Avoiding Conversion and Rearrangement Overhead in SIMD Architectures., International Journal of Parallel Programming 34(3): 237-260 (2006)
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, Limitations of special-purpose instructions for similarity measurements in media SIMD extensions., CASES 2006: 293-303
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, Improving the memory behavior of vertical filtering in the discrete wavelet transform., Conf. Computing Frontiers 2006: 253-260
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File., ISM 2006: 37-46
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Dynamic thermal clock skew compensation using tunable delay buffers., ISLPED 2006: 162-167
Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris, Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers., J. Low Power Electronics 2(3): 356-364 (2006)
Austen McDonald, JaeWoong Chung, Brian D. Carlstrom, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun, Architectural Semantics for Practical Transactional Memory., ISCA 2006: 53-65
Avi Mendelson, Memory management challenges in the power-aware computing era., ISMM 2006: 1-2
Babak Falsafi, T. N. Vijaykumar, Power-Aware Computer Systems: 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers (Lecture Notes in Computer Science), Power-Aware Computer Systems: 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers (Lecture Notes in Computer Science), Springer-Verlag New York, Inc., January 2006
Baker Abdalhaq, Ana Cortés, Tomàs Margalef, Germán Bianchini, Emilio Luque, Between classical and ideal: enhancing wildland fire prediction using cluster computing., Cluster Computing 9(3): 329-343 (2006)
Bart de Ruijsscher, Georgi Gaydadjiev, Jeroen Lichtenauer, Emile A. Hendriks, FPGA accelerator for real-time skin segmentation., ESTImedia 2006: 93-97
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten, Dynamic-SIMD for lens distortion compensation., ASAP 2006: 261-264
Bartosz Balis, Hong Linh Truong, Marian Bubak, Thomas Fahringer, Krzysztof Guzy, Kuba Rozkwitalski, An Instrumentation Infrastructure for Grid Workflow Applications., OTM Conferences (2) 2006: 1305-1314
Behnaz Pourebrahimi, Koen Bertels, G. M. Kandru, Stamatis Vassiliadis, Market-Based Resource Allocation in Grids., e-Science 2006: 80
Ben Rudiak-Gould, Alan Mycroft, Simon L. Peyton Jones, Haskell Is Not Not ML., ESOP 2006: 38-53
Bertrand Anckaert, Matias Madou, Koen De Bosschere, A Model for Self-Modifying Code., Information Hiding 2006: 232-248
Bilha Mendelson, Shlomit S. Pinter, Ayal Zaks, Introduction., International Journal of Parallel Programming 34(2): 111-112 (2006)
Bill Lin, Isaac Keslassy, The Concurrent Matching Switch Architecture., INFOCOM 2006
Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Hardware and a Tool Chain for ADRES., ARC 2006: 425-430
Bjorn De Sutter, Bruno De Bus, Koen De Bosschere, Bidirectional liveness analysis or how less than half of the Alpha's registers are used., Journal of Systems Architecture 52(10): 535-548 (2006)
Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili, MMR: A MultiMedia Router architecture to support hybrid workloads., J. Parallel Distrib. Comput. 66(2): 307-321 (2006)
Brian D. Carlstrom, Austen McDonald, Hassan Chafi, JaeWoong Chung, Chi Cao Minh, Christoforos E. Kozyrakis, Kunle Olukotun, The Atomos transactional programming language., PLDI 2006: 1-13
Brian D. Carlstrom, JaeWoong Chung, Hassan Chafi, Austen McDonald, Chi Cao Minh, Lance Hammond, Christoforos E. Kozyrakis, Kunle Olukotun, Executing Java programs with transactional memory., Sci. Comput. Program. 63(2): 111-129 (2006)
Burkhard Monien, Guang Gao, Horst Simon, Paul G. Spirakis, Per Stenström, Introduction., J. Parallel Distrib. Comput. 66(5): 615-616 (2006)
Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau, Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems., SiPS 2006: 280-285
Cagkan Erbas, Selin Cerav-Erbas, Andy D. Pimentel, Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design., IEEE Trans. Evolutionary Computation 10(3): 358-374 (2006)
Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten, A Monitoring-Aware Network-on-Chip Design Flow., DSD 2006: 97-106
Calin Ciordas, Kees Goossens, Andrei Radulescu, Twan Basten, NoC monitoring: impact on the design flow., ISCAS 2006
Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto, SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture., ERSA 2006: 63-69
Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto, Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC., IEEE Trans. Computers 55(5): 508-519 (2006)
Carlo Galuzzi, Elena Moscu Panainte, Yana Yankova, Koen Bertels, Stamatis Vassiliadis, Automatic selection of application-specific instruction-set extensions., CODES+ISSS 2006: 160-165
Carlos García, Manuel Prieto, Javier Setoain, Francisco Tirado, Enhancing the Performance of Multigrid Smoothers in Simultaneous Multithreading Architectures., VECPAR 2006: 439-451
Carmen Martínez, Enrique Vallejo, Ramón Beivide, Cruz Izu, Miquel Moretó, Dense Gaussian networks: suitable topologies for on-chip multiprocessors, International Journal of Parallel Programming , Volume 34 Issue 3, Kluwer Academic Publishers, June 2006
Carmen Martínez, Enrique Vallejo, Ramón Beivide, Cruz Izu, Miquel Moretó, Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors., International Journal of Parallel Programming 34(3): 193-211 (2006)
Catherine Dezan, Erwan Fabiani, Christophe Gouyen, Loïc Lagadec, Bernard Pottier, Caaliph Andriamisaina, Alix Poungou, Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques., Technique et Science Informatiques 25(7): 893-920 (2006)
Chaiyasit Manovit, Sudheendra Hangal, Hassan Chafi, Austen McDonald, Christos Kozyrakis, Kunle Olukotun, Testing implementations of transactional memory., PACT 2006: 134-143
Changhua Wu, Weihua Sheng, Wen-Zhan Song, A Dynamic MDS-Based Localization Algorithm for Mobile Sensor Networks., ROBIO 2006: 496-501
Chantal Ykman-Couvreur, Vincent Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal, Pareto-Based Application Specification for MP-SoC Customized Run-Time Management., ICSAMOS 2006: 78-84
Chengjun Zhu, Yuanxin Ouyang, Lei Gao, Zhenyong Chen, Zhang Xiong, An Automatic Video Text Detection Localization and Extraction Approach., SITIS 2006: 1-9
Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen, Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip., VLSI-SoC 2006: 80-85
Chris R. Jesshope, muTC - An Intermediate Language for Programming Chip Multiprocessors., Asia-Pacific Computer Systems Architecture Conference 2006: 147-160
Chris R. Jesshope, Microthreading a Model for Distributed Instruction-level Concurrency., Parallel Processing Letters 16(2): 209-228 (2006)
Chris R. Jesshope, Alexander V. Shafarenko, Special issue on Micro-grids - Guest Editor Introduction., International Journal of Parallel Programming 34(3): 189-192 (2006)
Chris R. Jesshope, Alexander V. Shafarenko, Guest Editor's Introduction (Part 2)., International Journal of Parallel Programming 34(4): 319-322 (2006)
Chris R. Jesshope, Colin Egan, Advances in Computer Systems Architecture 11th Asia-Pacific Conference ACSAC 2006 Shanghai China September 6-8 2006 Proceedings, Springer 2006
Christian Neeb, Norbert Wehn, Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip., DSD 2006: 665-672
Christine Nardini, Daniele Masotti, Sungroh Yoon, Enrico Macii, Michael D. Kuo, Giovanni De Micheli, Luca Benini, Mining Gene Sets for Measuring Similarities., ISCC 2006: 227-232
Christophe Poucet, David Atienza, Francky Catthoor, Template-Based Semi-Automatic Profiling of Multimedia Applications., ICME 2006: 1061-1064
Christos Koulamas, Aggeliki S. Prayati, Gauthier Lafruit, George Papadopoulos, Measurements and modeling of resource consumption in wireless video streaming: the decoder case., WMuNeP 2006: 67-72
Christos-Savvas Bouganis, Peter Y. K. Cheung, Li Zhaoping, FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex., FPL 2006: 1-6
Chuan Yue, Richard Tran Mills, Andreas Stathopoulos, Dimitrios S. Nikolopoulos, Runtime Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory., HPDC 2006: 183-194
Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk, Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation., ERSA 2006: 184-190
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo, Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs., FCCM 2006: 35-44
Claire Burguière, Christine Rochange, History-based Schemes and Implicit Path Enumeration., WCET 2006
Claudio Brunelli, Fabio Garzia, Jari Nurmi, A Coarse-Grain Reconfigurable Machine with Floating-Point Arithmetic Capabilities., ReCoSoC 2006: 1-7
Clemens Moser, Davide Brunelli, Lothar Thiele, Luca Benini, Lazy Scheduling for Energy Harvesting Sensor Nodes., DIPES 2006: 125-134
Clemens Moser, Lothar Thiele, Luca Benini, Davide Brunelli, Real-Time Scheduling with Regenerative Energy., ECRTS 2006: 261-270
Colin F. Snook, Michael Poppleton, Ian Johnson, Towards a Method for Rigorous Development of Generic Requirements Patterns., RODIN Book 2006: 326-342
Concepción Sanz, Manuel Prieto, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, System-level process variability compensation on memory organizations of dynamic applications: a case study., ISQED 2006: 376-382
Constantino G. Ribeiro, Marcelo Cintra, Quantifying Uncertainty in Points-To Relations., LCPC 2006: 190-204
Cor Meenderinck, Sorin Cotofana, Electron counting based high-radix multiplication in single electron tunneling technology., ISCAS 2006
Cor Meenderinck, Sorin Cotofana, High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology., SAMOS 2006: 447-456
Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Data-Driven Multithreading Using Conventional Microprocessors., IEEE Trans. Parallel Distrib. Syst. 17(10): 1176-1188 (2006)
Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Cacheflow: Cache Optimizations for Data Driven Multithreading., Parallel Processing Letters 16(2): 229-244 (2006)
Cristiana Bolchini, Carlo Curino, Fabio A. Schreiber, Letizia Tanca, Context Integration for Mobile Data Tailoring., MDM 2006: 5
Cristiana Bolchini, Carlo Curino, Fabio A. Schreiber, Letizia Tanca, Context integration for mobile data tailoring., SEBD 2006: 48-55
Cristiana Bolchini, Elisa Quintarelli, Context-Driven Data Filtering: A Methodology., OTM Workshops (2) 2006: 1986-1995
Cristiana Bolchini, Paolo Ferrandi, Pier Luca Lanzi, Fabio Salice, Evolving classifiers on field programmable gate arrays: Migrating XCS to FPGAs., Journal of Systems Architecture 52(8-9): 516-533 (2006)
Cruz Izu, José Miguel-Alonso, José A. Gregorio, Effects of Injection Pressure on Network Throughput., PDP 2006: 91-98
Cyril Banino-Rokkones, Olivier Beaumont, Lasse Natvig, Master-Slave Tasking on Asymmetric Networks., Euro-Par 2006: 167-176
Dan Tsafrir, Dror G. Feitelson, The Dynamics of Backfilling: Solving the Mystery of Why Increased Inaccuracy May Help., IISWC 2006: 131-141
Dan Tsafrir, Dror G. Feitelson, Instability in parallel job scheduling simulation: the role of workload flurries., IPDPS 2006
Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren, Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors., ICS 2006: 145-155
Daniel Gracia Pérez, Hugues Berry, Olivier Temam, A Sampling Method Focusing on Practicality., IEEE Micro 26(6): 14-28 (2006)
Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala, Software Implementation of WiMAX on the Sandbridge SandBlaster Platform., SAMOS 2006: 435-446
Daniel Ziener, Stefan Assmus, Jürgen Teich, Identifying FPGA IP-Cores Based on Lookup Table Content Analysis., FPL 2006: 1-6
Daniele Masotti, Elisa Ficarra, Enrico Macii, Luca Benini, Optimized Technique for Dna Structural Properties Discovering., International Journal on Artificial Intelligence Tools 15(5): 695-710 (2006)
David Atienza, Jose Manuel Mendias, Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor, Systematic dynamic memory management design methodology for reduced memory footprint., ACM Trans. Design Autom. Electr. Syst. 11(2): 465-489 (2006)
David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip., DAC 2006: 618-623
David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo, Compiler-Driven Leakage Energy Reduction in Banked Register Files., PATMOS 2006: 107-116
David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris, Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems., Integration 39(2): 113-130 (2006)
David B. Thomas, Wayne Luk, Efficient Hardware Generation of Random Variates with Arbitrary Distributions., FCCM 2006: 57-66
David B. Thomas, Wayne Luk, Non-Uniform Random Number Generation Through Piecewise Linear Approximations., FPL 2006: 1-6
David F. Bacon, Perry Cheng, Daniel Frampton, David Grove, Matthias Hauswirth, V. T. Rajan, Demonstration: On-Line Visualization and Analysis of Real-Time Systems with TuningFork., CC 2006: 96-100
David Gregg, M. Anton Ertl, Optimizing code-copying JIT compilers for virtual stack machines., Concurrency and Computation: Practice and Experience 18(11): 1465-1484 (2006)
David J. Pearce, Paul H. J. Kelly, A dynamic topological sort algorithm for directed acyclic graphs., ACM Journal of Experimental Algorithmics 11: (2006)
David Montaner, Joaquín Tárraga, Jaime Huerta-Cepas, Jordi Burguet-Castell, Juan M. Vaquerizas, Lucía Conde, Pablo Minguez, Javier Vera, Sach Mukherjee, Joan Valls, Miguel A. G. P, Next station in microarray data analysis: GEPAS., Nucleic Acids Research 34(Web-Server-Issue): 486-491 (2006)
David Ródenas, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, George Almási, Călin Caşcaval, José Castaños, José Moreira, Exploiting multilevel parallelism using OpenMP on a massive multithreaded architecture, Journal of Embedded Computing , Volume 2 Issue 2, IOS Press, April 2006
David Verstraeten, Benjamin Schrauwen, Dirk Stroobandt, Reservoir-based techniques for speech recognition., IJCNN 2006: 1050-1053
Davide Brunelli, Elisabetta Farella, Laura Rocchi, Marco Dozza, Lorenzo Chiari, Luca Benini, Bio-feedback System for Rehabilitation Based on a Wireless Body Area Network., PerCom Workshops 2006: 527-531
Davy Genbrugge, Lieven Eeckhout, Koen De Bosschere, Accurate memory data flow modeling in statistical simulation., ICS 2006: 87-96
Derin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici, A Predictable Communication Scheme for Embedded Multiprocessor Systems., VLSI-SoC 2006: 152-157
Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers, Offset assignment using simultaneous variable coalescing., ACM Trans. Embedded Comput. Syst. 5(4): 864-883 (2006)
Diana Göhringer, Mateusz Majer, Jürgen Teich, Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine., Dynamically Reconfigurable Architectures 2006
Diego Andrade, Basilio B. Fraguela, Ramon Doallo, Cache Behavior Modelling for Codes Involving Banded Matrices., LCPC 2006: 205-219
Diego Andrade, Basilio B. Fraguela, Ramon Doallo, Analytical modeling of codes with arbitrary data-dependent conditional structures., Journal of Systems Architecture 52(7): 394-410 (2006)
Diego R. Llanos Ferraris, TPCC-UVa: an open-source TPC-C implementation for global performance measurement of computer systems., SIGMOD Record 35(4): 6-15 (2006)
Diego R. Llanos Ferraris, Belén Palop, TPCC-UVa: an open-source TPC-C implementation for parallel and distributed systems., IPDPS 2006
Diego Sevilla, José M. García, Antonio Gómez, Automatic Code Generation for Non-Funtional Aspects in the CORBA-LC Component Model., ICUC 2006
Dionisios N. Pnevmatikatos, Aggelos Arelakis, Variable-Length Hashing for Exact Pattern Matching., FPL 2006: 1-6
Dirk Koch, Matthiaas Koerber, Jürgen Teich, Searching RC5-Keys with Distributed Reconfigurable Computing., ERSA 2006: 42-48
Dirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt, Jürgen Teich, An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks., ARCS 2006: 202-216
Djemai Kebbal, Pascal Sainrat, Combining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis., WCET 2006
Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich, A Generic Framework for Rapid Prototyping of System-on-Chip Designs., CDES 2006: 189-195
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template., ReCoSoC 2006: 31-37
Domenico Talia, Angelos Bilas, Marios D. Dikaiakos, Knowledge and Data Management in GRIDs, Knowledge and Data Management in GRIDs, Springer-Verlag New York, Inc., November 2006
Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque, A Reconfigurable Data Cache for Adaptive Processors., ARC 2006: 230-242
Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque, Evaluation of the field-programmable cache: performance and energy consumption., Conf. Computing Frontiers 2006: 361-372
Don M. Dini, Michael van Lent, Paul Carpenter, K. Iyer, Building Robust Planning and Exection Systems for Virtual Worlds., AIIDE 2006: 29-35
Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee, Reducing energy of virtual cache synonym lookup using bloom filters., CASES 2006: 179-189
Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides, Accuracy-Guaranteed Bit-Width Optimization., IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1990-2000 (2006)
Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong, A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis., IEEE Trans. Computers 55(6): 659-671 (2006)
Dorit Nuzman, Ira Rosen, Ayal Zaks, Auto-vectorization of interleaved data for SIMD., PLDI 2006: 132-143
Dorit Nuzman, Richard Henderson, Multi-platform Auto-vectorization., CGO 2006: 281-294
Dragan Stojanovic, Book Reviews: Web Service-Oriented Project Development from Different Perspectives, IEEE Distributed Systems Online , Volume 7 Issue 2, IEEE Educational Activities Department, February 2006
Dries Buytaert, Jonas Maebe, Lieven Eeckhout, Koen De Bosschere, Building Java program analysis tools using Javana., OOPSLA Companion 2006: 653-654
Dror Feitelson, Eitan Frachtenberg, Larry Rudolph, Uwe Schwiegelshohn, Job Scheduling Strategies for Parallel Processing: 11th International Workshop, JSSPP 2005, Cambridge, MA, USA, June 19, 2005, Revised Selected Papers (Lecture Notes in Computer Science), Job Scheduling Strategies for Parallel Processing: 11th International Workshop, JSSPP 2005, Cambridge, MA, USA, June 19, 2005, Revised Selected Papers (Lecture Notes in Computer Science), Springer-Verlag New York, Inc., January 2006
Dror G. Feitelson, Metrics for Mass-Count Disparity., MASCOTS 2006: 61-68
Dror G. Feitelson, Dan Tsafrir, Workload sanitation for performance evaluation., ISPASS 2006: 221-230
Dror G. Feitelson, Gillian Z. Heller, Stephen R. Schach, An Empirically-Based Criterion for Determining the Success of an Open-Source Project., ASWEC 2006: 363-368
Edi Shmueli, Dror G. Feitelson, Using Site-Level Modeling to Evaluate the Performance of Parallel System Schedulers., MASCOTS 2006: 167-178
Eduard Ayguadé, Gerald Baumgartner, J. Ramanujam, P. Sadayappan, Languages and Compilers for Parallel Computing 18th International Workshop LCPC 2005 Hawthorne NY USA October 20-22 2005 Revised Selected Papers, Springer 2006
Eduard Ayguadé, Marc González, Xavier Martorell, Gabriele Jost, Employing nested OpenMP for the parallelization of multi-zone computational fluid dynamics applications., J. Parallel Distrib. Comput. 66(5): 686-697 (2006)
Eduard Ayguadé, Wolfgang Karl, Koen De Bosschere, Jean-Francois Collard, Topic 7: Parallel Computer Architecture and Instruction Level Parallelism., Euro-Par 2006: 459
Eduardo Argollo, Adriana Gaudiani, Dolores Rexachs, Emilio Luque, Tuning Application in a Multi-cluster Environment., Euro-Par 2006: 78-88
Eduardo César, A. Moreno, Joan Sorribes, Emilio Luque, Modeling Master/Worker applications for automatic performance tuning., Parallel Computing 32(7-8): 568-589 (2006)
Edwin V. Bonilla, Christopher K. I. Williams, Felix V. Agakov, John Cavazos, John Thomson, Michael F. P. O'Boyle, Predictive search distributions., ICML 2006: 121-128
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Parallel Memory Architecture for Arbitrary Stride Accesses., DDECS 2006: 65-70
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Parallel Memory Implementation for Arbitrary Stride Accesses., ICSAMOS 2006: 1-6
Eero Wallenius, Timo Hämäläinen, Timo Nihtilä, Jani Puttonen, Jyrki Joutsensalo, Simulation Study on 3G and WLAN Inter-Working., IEICE Transactions 89-B(2): 446-459 (2006)
Electra Tamani, Paraskevas Evripidou, Applying Trust Mechanisms in an agent-based P2P Network of Service Providers and Requestors., CCGRID 2006: 13
Electra Tamani, Paraskevas Evripidou, A Pragmatic and Pervasive Methodology to Web Service Discovery., OTM Workshops (2) 2006: 1285-1294
Eleftheria Katsiri, Alan Mycroft, Applying Bayesian Networks to Sensor-Driven Systems., ISWC 2006: 149-150
Eleftherios Tiakas, Apostolos N. Papadopoulos, Alexandros Nanopoulos, Yannis Manolopoulos, Dragan Stojanovic, Slobodanka Djordjevic-Kajan, Trajectory Similarity Search in Spatial Networks, IDEAS '06: Proceedings of the 10th International Database Engineering and Applications Symposium, IEEE Computer Society, December 2006
Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis, Compiler-driven FPGA-area allocation for reconfigurable computing., DATE 2006: 369-374
Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis, Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration., VLSI Signal Processing 43(2-3): 161-172 (2006)
Elias Athanasopoulos, Kostas G. Anagnostakis, Evangelos P. Markatos, Misusing Unstructured P2P Systems to Perform DoS Attacks: The Network That Never Forgets., ACNS 2006: 130-145
Elisa Ficarra, Enrico Macii, Giovanni De Micheli, Luca Benini, Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images., CBMS 2006: 413-418
Elisabetta Farella, Augusto Pieracci, Luca Benini, Andrea Acquaviva, A Wireless Body Area Sensor Network for Posture Detection., ISCC 2006: 454-459
Elisabetta Farella, M. Sile O'Modhrain, Luca Benini, Bruno Riccò, Gesture Signature for Ambient Intelligence Applications: A Feasibility Study., Pervasive 2006: 288-304
Eric Petit, François Bodin, Guillaume Papaure, Florence Dru, Poster reception - ASTEX: a hot path based thread extractor for distributed memory system on a chip., SC 2006: 141
Erik Berg, Håkan Zeffer, Erik Hagersten, A statistical multiprocessor cache model., ISPASS 2006: 89-99
Erno Salminen, Tero Kangas, Timo D. Hämäläinen, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, HIBI Communication Network for System-on-Chip., VLSI Signal Processing 43(2-3): 185-205 (2006)
Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis, Nectarios Koziris, Exploring the Capacity of a Modern SMT Architecture to Deliver High Scientific Application Performance., HPCC 2006: 180-189
Evangelos Koukis, Nectarios Koziris, Memory and Network Bandwidth Aware Scheduling of Multiprogrammed Workloads on Clusters of SMPs., ICPADS (1) 2006: 345-354
Fátima Al-Shahrour, Pablo Minguez, Joaquín Tárraga, David Montaner, Eva Alloza, Juan M. Vaquerizas, Lucía Conde, Christian Blaschke, Javier Vera, Joaquín Dopazo, BABELOMICS: a systems biology perspective in the functional annotation of genome-scale experiments., Nucleic Acids Research 34(Web-Server-Issue): 472-476 (2006)
Félix Tobajas, Roberto Esper-Chaín, Raúl Regidor, O. Santana, Roberto Sarmiento, A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology., DDECS 2006: 21-26
F. Bagci, H. Schick, J. Petzold, W. Trumler, T. Ungerer, The reflective mobile agent paradigm implemented in a smart office environment, Personal and Ubiquitous Computing , Volume 11 Issue 1, Springer-Verlag, October 2006
F. Blachot, Benoît Dupont de Dinechin, Guillaume Huard, SCAN: A Heuristic for Near-Optimal Software Pipelining., Euro-Par 2006: 289-298
Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenzo Rana, Marco D. Santambrogio, VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow., IPDPS 2006
Fabrizio Petrini, Olav Lysne, Ron Brightwell, Guest Editors' Introduction: High-Performance Interconnects., IEEE Micro 26(3): 7-9 (2006)
Fadia Nemer, Hugues Cassé, Pascal Sainrat, Jean Paul Bahsoun, Marianne De Michiel, PapaBench: a Free Real-Time Benchmark., WCET 2006
Farrukh Nadeem, Muhammad Murtaza Yousaf, Radu Prodan, Thomas Fahringer, Soft Benchmarks-Based Application Performance Prediction Using a Minimum Training Set., e-Science 2006: 71
Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli, Reliability Support for On-Chip Memories Using Networks-on-Chip., ICCD 2006
Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini, An integrated open framework for heterogeneous MPSoC design space exploration., DATE 2006: 1145-1150
Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo, Contrasting a NoC and a traditional interconnect fabric with layout awareness., DATE 2006: 124-129
Felipe Cabarcas, Richard Demo Souza, Javier Garcia-Frias, Turbo coding of strongly nonuniform memoryless sources with unequal energy allocation and PAM signaling., IEEE Transactions on Signal Processing 54(5): 1942-1946 (2006)
Felix V. Agakov, Edwin V. Bonilla, John Cavazos, Björn Franke, Grigori Fursin, Michael F. P. O'Boyle, John Thomson, Marc Toussaint, Christopher K. I. Williams, Using Machine Learning to Focus Iterative Optimization., CGO 2006: 295-305
Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado, A Load-Store Queue Design Based on Predictive State Filtering., J. Low Power Electronics 2(1): 27-36 (2006)
Fernando Castro, Luis Piñuel, Daniel Chaver, Manuel Prieto, Michael C. Huang, Francisco Tirado, DMDC: Delayed Memory Dependence Checking through Age-Based Filtering., MICRO 2006: 297-308
Fernando Guirado, Ana Ripoll, Concepció Roig, Aura Hernandez, Emilio Luque, Exploiting Throughput for Pipeline Execution in Streaming Image Processing Applications., Euro-Par 2006: 1095-1105
Filipa Duarte, Stephan Wong, Profiling Bluetooth and Linux on the Xilinx Virtex II Pro., DSD 2006: 229-235
Florent Bouchez, Alain Darte, Christophe Guillon, Fabrice Rastello, Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How., LCPC 2006: 283-298
Florentin Picioroaga, Uwe Brinkschulte, Flexible QoS management and real-time in OSA+ middleware., PDPTA 2006: 984-990
Florin Isaila, David E. Singh, Jesús Carretero, Félix García, On Evaluating Decentralized Parallel I/O Scheduling Strategies for Parallel File Systems., VECPAR 2006: 120-130
Florin Isaila, David E. Singh, Jesús Carretero, Félix García, Gabor Szeder, Thomas Moschny, Integrating Logical and Physical File Models in the MPI-IO Implementation for "Clusterfile"., CCGRID 2006: 462
Francesc Guim, Ivan Rodero, Julita Corbalán, Jesús Labarta, Ariel Oleksiak, Tomasz Kuczynski, Dawid Szejnfeld, Jarek Nabrzyski, Uniform Job Monitoring using the HPC-Europa Single Point of Access., CCGRID 2006: 55
Francesc Guim, Ivan Rodero, M. Tomas, Julita Corbalán, Jesús Labarta, The Palantir Grid Meta-Information System., GRID 2006: 329-330
Francesco Belletti, Sebastiano Fabio Schifano, Raffaele Tripiccione, François Bodin, Philippe Boucaud, Jacques Micheli, Olivier Pène, Nicola Cabibbo, Sergio de Luca, Alessandro Lonardo, , Computing for LQCD: apeNEXT., Computing in Science and Engineering 8(1): 18-29 (2006)
Francesco Bruschi, Fabrizio Ferrandi, A SystemC-based Framework of Communication Architecture., FDL 2006: 319-327
Francesco Nerieri, Radu Prodan, Thomas Fahringer, Hong Linh Truong, Overhead Analysis of Grid Workflow Applications., GRID 2006: 17-24
Francesco Rossi, Massimo Rovini, Luca Fanucci, Design and Validation of Digital Channels for a Galileo Receiver Prototype., DSD 2006: 545-549
Francisco Almeida, Sergio Barrachina, Vicente Blanco Pérez, E. Quintana, Adrián Santos, An Open Source Web Service Based Platform for Heterogeneous Clusters., ISPA 2006: 760-771
Francisco Almeida, Sergio Barrachina, Vicente Blanco Pérez, Enrique S. Quintana-Ortí, Adrián Santos, An Open Source Web Service Based Platform for Heterogeneous Clusters., ISPA 2006: 760-771
Francisco Delicado, Pedro Cuenca, Luis Orozco-Barbosa, QoS-Aware Video Communications over TDMA/TDD Wireless Networks., PWC 2006: 50-63
Francisco Delicado, Pedro Cuenca, Luis Orozco-Barbosa, QoS mechanisms for multimedia communications over TDMA/TDD WLANs., Computer Communications 29(13-14): 2721-2735 (2006)
Francisco Gilabert, María Engracia Gómez, Pedro López, José Duato, On the Influence of the Selection Function on the Performance of Fat-Trees., Euro-Par 2006: 864-873
Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero, Predictable Performance in SMT Processors: Synergy between the OS and SMTs., IEEE Trans. Computers 55(7): 785-799 (2006)
Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata, Pipelined Range Reduction for Floating Point Numbers., ASAP 2006: 145-152
Francisco J. Villa, Manuel E. Acacio, José M. García, On the Evaluation of Dense Chip-Multiprocessor Architectures., ICSAMOS 2006: 21-27
Frank Hannig, Hritam Dutta, Jürgen Teich, Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology., IJES 2(1/2): 114-127 (2006)
Frank Kienle, Timo Lehnigk-Emden, Norbert Wehn, Fast convergence algorithm for LDPC Codes., VTC Spring 2006: 2393-2397
Frank Olaf Sem-Jacobsen, Olav Lysne, Tor Skeie, Combining Source Routing and Dynamic Fault Tolerance., SBAC-PAD 2006: 151-158
Frank Olaf Sem-Jacobsen, Tor Skeie, Olav Lysne, José Duato, Dynamic Fault Tolerance with Misrouting in Fat Trees., ICPP 2006: 33-44
Frederic Worm, Patrick Thiran, Paolo Ienne, Designing Robust Checkers in the Presence of Massive Timing Errors., IOLTS 2006: 281-286
Fredrik Dahlgren, Partial Continuous Functions and Admissible Domain Representations., CiE 2006: 94-104
Fredrik Warg, Per Stenström, Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush., SBAC-PAD 2006: 91-98
Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures., FPL 2006: 1-8
Friman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero, Performance Analysis of Sequence Alignment Applications., IISWC 2006: 51-60
Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis, Networks on chips for high-end consumer-electronics TV system architectures., DATE Designers' Forum 2006: 148-153
Gabriel Rodríguez, María J. Martín, Patricia González, Juan Touriño, Controller/Precompiler for Portable Checkpointing., IEICE Transactions 89-D(2): 408-417 (2006)
Gamal Atallah, Gabriel Rodríguez, Indirectpatent citations., Scientometrics 67(3): 437-465 (2006)
Ganesh Bikshandi, Jia Guo, Christoph von Praun, Gabriel Tanase, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Lawrence Rauchwerger, Design and Use of htalib - A Library for Hierarchically Tiled Arrays., LCPC 2006: 17-32
Ganesh Bikshandi, Jia Guo, Daniel Hoeflinger, Gheorghe Almási, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Christoph von Praun, Programming for parallelism and locality with hierarchically tiled arrays., PPOPP 2006: 48-57
Gary Wang, Zoran Salcic, Morteza Biglari-Abhari, Customizing multiprocessor implementation of an automated video surveillance system, EURASIP Journal on Embedded Systems , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Gaspar Mora, Jose Flich, José Duato, Pedro López, Elvira Baydal, Olav Lysne, Towards an efficient switch architecture for high-radix switches., ANCS 2006: 11-20
Genaro Costa, Anna Morajko, Tomàs Margalef, Emilio Luque, Automatic Tuning in Computational Grids., PARA 2006: 381-389
George A. Papadopoulos, Aristos Stavrou, Odysseas Papapetrou, An implementation framework for software architectures based on the coordination paradigm, Science of Computer Programming , Volume 60 Issue 1, Elsevier North-Holland, Inc., March 2006
Georgi Gaydadjiev, C. John Glossner, Jarmo Takala, Stamatis Vassiliadis, Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (IC-SAMOS 2006) Samos Greece July 17-20 2006, IEEE 2006
Georgi Gaydadjiev, Stamatis Vassiliadis, SAD Prefetching for MPEG4 Using Flux Caches., SAMOS 2006: 248-258
Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis, Multimedia rectangularly addressable memory., IEEE Transactions on Multimedia 8(2): 315-322 (2006)
Georgios I. Goumas, Nikolaos Drosinos, Maria Athanasaki, Nectarios Koziris, Message-passing code generation for non-rectangular tiling transformations., Parallel Computing 32(10): 711-732 (2006)
Georgios Keramidas, Konstantinos Aisopos, Stefanos Kaxiras, Dynamic Dictionary-Based Data Compression for Level-1 Caches., ARCS 2006: 114-129
Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios N. Serpanos, Preventing Denial-of-Service Attacks in Shared CMP Caches., SAMOS 2006: 359-372
Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, Paul M. Heysters, Efficient architectures for streaming applications., Dynamically Reconfigurable Architectures 2006
Gerard K. Rauwerda, Gerard J. M. Smit, Casper R. W. van Benthem, Paul M. Heysters, Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture., ERSA 2006: 110-116
Gerardo Fernández, Pedro Cuenca, Luis Orozco-Barbosa, Hari Kalva, Very low complexity MPEG-2 to H.264 transcoding using machine learning., ACM Multimedia 2006: 931-940
Gerardo Fernández-Escribano, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, Speeding-Up the Macroblock Partition Mode Decision in MPEG-2/H.264 Transcoding., ICIP 2006: 869-872
Gerardo Fernández-Escribano, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, RD-Optimization for MPEG-2 to H.264 Transcoding., ICME 2006: 309-312
Germán Bianchini, Ana Cortés, Tomàs Margalef, Emilio Luque, Improved Prediction Methods for Wildfires Using High Performance Computing: A Comparison., International Conference on Computational Science (1) 2006: 539-546
Giacomo Paci, Paul Marchal, Francesco Poletti, Luca Benini, Exploring "temperature-aware" design in low-power MPSoCs., DATE 2006: 838-843
Gianluca Casarosa, Michele Apuzzo, Luca Fanucci, Bruno Sarti, Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites., DSD 2006: 338-345
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos, An Energy-Delay Efficient Subword Permutation Unit., ASAP 2006: 245-252
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos, Fast bit permutation unit for media enhanced microprocessors., ISCAS 2006
Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto, Synthesis of Object Oriented Models on Reconfigurable Hardware., ERSA 2006: 249-250
Giovanni Agosta, Marco D. Santambrogio, Seda Ogrenci Memik, Adaptive Metrics for System-Level Functional Partitioning., FDL 2006: 153-155
Giovanni Agosta, Stefano Crespi Reghizzi, Dario Domizioli, Martino Sykora, Global instruction scheduling in dynamic compilation for embedded systems, JTRES '06: Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems, ACM, October 2006
Giovanni Agosta, Stefano Crespi Reghizzi, Gabriele Svelto, Jelatine: a virtual machine for small embedded systems, JTRES '06: Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems, ACM, October 2006
Giovanni Beltrame, Dario Bruschi, Donatella Sciuto, Cristina Silvano, Decision-theoretic exploration of multiProcessor platforms., CODES+ISSS 2006: 205-210
Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington, Exploiting TLM and object introspection for system-level simulation., DATE 2006: 100-105
Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane, An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures., VLSI-SoC 2006: 146-151
Giovanni Busonera, Salvatore Carta, Andrea Marongiu, Luigi Raffo, Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information., DSD 2006: 265-268
Giovanni De Micheli, Luca Benini, Networks on Chips: Technology and Tools (Systems on Silicon), Networks on Chips: Technology and Tools (Systems on Silicon), Morgan Kaufmann Publishers Inc., July 2006
Girma S. Tewolde, Weihua Sheng, Ant Colony Optimization for Tool Path Integration in Spray Forming Processes., IROS 2006: 2394-2399
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design., ICSAMOS 2006: 115-122
Giuseppe Ascia, Vincenzo Catania, Daniela Panno, An integrated fuzzy-GA approach for buffer management., IEEE T. Fuzzy Systems 14(4): 528-541 (2006)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip., J. UCS 12(4): 370-394 (2006)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti, Neighbors-on-Path: A New Selection Strategy for On-Chip Networks., ESTImedia 2006: 79-84
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti, A new selection policy for adaptive routing in network on chip, EHAC'06: Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications, World Scientific and Engineering Academy and Society (WSEAS), February 2006
Grzegorz Danilewicz, Wojciech Kabacinski, Comments on "Wide-sense nonblocking multicast Log/sub 2/(N m p) Networks"., IEEE Transactions on Communications 54(6): 980-982 (2006)
Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk, I. Demirkiran, Compiler-Directed Management of Leakage Power in Software-Managed Memories., ISVLSI 2006: 450-451
Guangyu Chen, Feihui Li, Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu, Leakage-Aware SPM Management., ISVLSI 2006: 393-398
Guido Bertoni, Luca Breveglieri, Farina Roberto, Francesco Regazzoni, Speeding Up AES By Extending a 32 bit Processor Instruction Set., ASAP 2006: 275-282
Guilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Mustafa Karaköy, Dynamic scratch-pad memory management for irregular array access patterns., DATE 2006: 931-936
Guillaume Chelius, Antoine Fraboulet, Eric Fleury, Demonstration of worldsens: a fast prototyping and performance evaluation of wireless sensor network applications & protocols, REALMAN '06: Proceedings of the 2nd international workshop on Multi-hop ad hoc networks: from theory to reality, ACM, May 2006
Guillermo L. Taboada, Juan Touriño, Ramon Doallo, Non-blocking Java Communications Support on Clusters., PVM/MPI 2006: 256-265
Guillermo L. Taboada, Juan Touriño, Ramon Doallo, Efficient Java Communication Protocols on High-speed Cluster Interconnects., LCN 2006: 264-271
Gustavo M. Callicó, Rafael Peset Llopis, Sebastian López, José Fco. López, Antonio Núñez, Ramanathan Sethuraman, Roberto Sarmiento, Low-cost super-resolution algorithms implementation over a HW/SW video compression platform, EURASIP Journal on Applied Signal Processing , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Håkan Zeffer, Zoran Radovic, Erik Hagersten, Exploiting locality: a flexible DSM approach., IPDPS 2006
Håkan Zeffer, Zoran Radovic, Martin Karlsson, Erik Hagersten, TMA: a trap-based memory architecture., ICS 2006: 259-268
Haakon Dybdahl, Marius Grannæs, Lasse Natvig, Cache Write-Back Schemes for Embedded Destructive-Read DRAM., ARCS 2006: 145-159
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig, Destructive-read in embedded DRAM, impact on power consumption, Journal of Embedded Computing , Volume 2 Issue 2, IOS Press, April 2006
Haakon Dybdahl, Per Stenström, Lasse Natvig, An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches, MEDEA '06: Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, ACM, September 2006
Haakon Dybdahl, Per Stenström, Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination., Asia-Pacific Computer Systems Architecture Conference 2006: 52-66
Haakon Dybdahl, Per Stenström, Lasse Natvig, A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors., HiPC 2006: 22-34
Hadda Cherroun, Alain Darte, Paul Feautrier, Scheduling under resource constraints using dis-equations., DATE 2006: 1067-1072
Hagit Attiya, David Hay, Isaac Keslassy, Packet-mode emulation of output-queued switches., SPAA 2006: 138-147
Hagit Attiya, Faith Ellen, Panagiota Fatourou, The Complexity of Updating Multi-writer Snapshot Objects., ICDCN 2006: 319-330
Hakduran Koc, Ozcan Ozturk, Mahmut T. Kandemir, Sri Hari Krishna Narayanan, Ehat Ercanli, Minimizing energy consumption of banked memories using data recomputation., ISLPED 2006: 358-362
Hakduran Koc, Suleyman Tosun, Ozcan Ozturk, Mahmut T. Kandemir, Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems., ISVLSI 2006: 448-449
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter P. Jonker, Run-time reconfiguration of communication in SIMD architectures., IPDPS 2006
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard Kleihorst, RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications, Journal of Embedded Computing , Volume 2 Issue 2, IOS Press, April 2006
Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, An interprocedural code optimization technique for network processors using hardware multi-threading support., DATE 2006: 919-924
Hans Peter Löb, Rainer Buchty, Wolfgang Karl, A network agent for diagnosis and analysis of real-time Ethernet networks., CASES 2006: 65-73
Hans Vandierendonck, Koen De Bosschere, On the Impact of OS and Linker Effects on Level-2 Cache Performance., MASCOTS 2006: 87-95
Hans Vandierendonck, Pedro Trancoso, Building and Validating a Reduced TPC-H Benchmark., MASCOTS 2006: 383-392
Hans Vandierendonck, Philippe Manet, Jean-Didier Legat, Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses., DATE 2006: 357-362
Haris Lekatsas, Jorg Henkel, Venkata Jakkula, Srimat Chakradhar, Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems, VLSID '06: Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design, IEEE Computer Society, January 2006
Hassan Ghasemzadeh, Sepideh Sepideh Mazrouee, Mohammad Reza Kakoee, Modified Pseudo LRU Replacement Algorithm., ECBS 2006: 368-376
Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout, Pattern-driven prefetching for multimedia applications on embedded processors., Journal of Systems Architecture 52(4): 199-212 (2006)
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, Single phase clock scheme for mobile logic gates, Electronic Letters vol. 42 no. 24, pp. 1382-1383
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, Single Phase Clock Scheme for Mobile Based Circuits, XXI Conf. on Design of Circuits and Integrated Syst.
Heikki Kariniemi, Jari Nurmi, Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip., DDECS 2006: 186-191
Heikki Kariniemi, Jari Nurmi, On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips., FPL 2006: 1-6
Heiner Giefers, Achim Rettberg, Energy aware multiple clock domain scheduling for a bit-serial self-timed architecture., SBCCI 2006: 113-118
Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert, Toward architecture-based test-vector generation for timing verification of fast parallel multipliers., IEEE Trans. VLSI Syst. 14(4): 370-379 (2006)
Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, D. Johansson, M. Scholin, Multiplier reduction tree with logarithmic logic depth and regular connectivity., ISCAS 2006
Herbert Leitold, Evangelos P. Markatos, Communications and Multimedia Security 10th IFIP TC-6 TC-11 International Conference CMS 2006 Heraklion Crete Greece October 19-21 2006 Proceedings, Springer 2006
Hong Linh Truong, Peter Brunner, Thomas Fahringer, Francesco Nerieri, Robert Samborski, Bartosz Balis, Marian Bubak, Kuba Rozkwitalski, K-WfGrid Distributed Monitoring and Performance Analysis Services for Workflows in the Grid., e-Science 2006: 15
Hong Linh Truong, Robert Samborski, Thomas Fahringer, Towards a Framework for Monitoring and Analyzing QoS Metrics of Grid Services., e-Science 2006: 65
Hongyu Yang, Feng Xie, Yi Lu, Network Anomalous Attack Detection Based on Clustering and Classifier., CIS 2006: 672-682
Hongyu Yang, Feng Xie, Yi Lu, Clustering and Classification Based Anomaly Detection., FSKD 2006: 1082-1091
Hritam Dutta, Frank Hannig, Jürgen Teich, Controller Synthesis for Mapping Partitioned Programs on Array Architectures., ARCS 2006: 176-190
Hritam Dutta, Frank Hannig, Jürgen Teich, Hierarchical Partitioning for Piecewise Linear Algorithms., PARELEC 2006: 153-160
Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger, A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing., ASAP 2006: 331-340
I. Artundo, D. Manjarres, Wim Heirman, Christof Debaes, Joni Dambre, Jan M. Van Campenhout, Hugo Thienpont, Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior., ISPA Workshops 2006: 311-321
Ian Bell, Nabil Hasasneh, Chris R. Jesshope, Supporting Microthread Scheduling and Synchronisation in CMPs., International Journal of Parallel Programming 34(4): 343-381 (2006)
Ian Watson, Jens Trotzky, Self-organising Hierarchical Retrieval in a Case-Agent System., ECCBR 2006: 62-75
Idit Keidar, Assaf Schuster, Want scalable computing?: speculate!, SIGACT News 37(3): 59-66 (2006)
Ilya Obridko, Ran Ginosar, Minimal Energy Asynchronous Dynamic Adders., IEEE Trans. VLSI Syst. 14(9): 1043-1047 (2006)
Ingebjørg Theiss, Olav Lysne, FRoots: A Fault Tolerant and Topology-Flexible Routing Technique., IEEE Trans. Parallel Distrib. Syst. 17(10): 1136-1150 (2006)
Ioannis Sourdis, Vassilis Dimopoulos, Dionisios N. Pnevmatikatos, Stamatis Vassiliadis, Packet pre-filtering for network intrusion detection., ANCS 2006: 183-192
Iouliia Skliarova, Intelligent Systems Engineering with Reconfigurable Computing., IFIP PPAI 2006: 161-170
Isabelle Linden, Jean-Marie Jacquet, Koen De Bosschere, Antonio Brogi, On the expressiveness of timed coordination models., Sci. Comput. Program. 61(2): 152-187 (2006)
Ivan Rodero, Francesc Guim, Julita Corbalán, Jesús Labarta, How the JSDL can Exploit the Parallelism?, CCGRID 2006: 275-282
Ivona Brandic, Sabri Pllana, Siegfried Benkner, Amadeus: A Holistic Service-oriented Environment for Grid Workflows., GCC Workshops 2006: 259-266
Ivona Brandic, Sabri Pllana, Siegfried Benkner, An approach for the high-level specification of QoS-aware grid workflows considering location affinity., Scientific Programming 14(3-4): 231-250 (2006)
Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson, MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis., Conf. Computing Frontiers 2006: 21-28
Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev, A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration., DAC 2006: 125-130
Izchak Sharfman, Assaf Schuster, Daniel Keren, A geometric approach to monitoring threshold functions over distributed data streams., SIGMOD Conference 2006: 301-312
Júlio C. B. de Mattos, Stephan Wong, Luigi Carro, The Molen FemtoJava Engine., ASAP 2006: 19-22
Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas, 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures., Dynamically Reconfigurable Architectures 2006
Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas, 06141 Executive Summary -- Dynamically Reconfigurable Architectures., Dynamically Reconfigurable Architectures 2006
Jürgen Becker, Kurt Brändle, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl, Thorsten Köster, Michael Wenz, Heinz Wörn, Digital On-Demand Computing Organism for Real-Time Systems., ARCS Workshops 2006: 230-245
Jürgen Hofer, Thomas Fahringer, Specification-based Synthesis of Tailor-made Grid Service Wrappers for Scientific Legacy Codes., GRID 2006: 305-306
Jürgen Hofer, Thomas Fahringer, Presenting Scientific Legacy Programs as Grid Services via Program Synthesis., e-Science 2006: 34
Jürgen Teich, Are current ESL tools meeting the requirements of advanced embedded systems?, CODES+ISSS 2006: 166
Jürgen Teich, Shuvra S. Bhattacharyya, Analysis of Dataflow Programs with Interval-limited Data-rates., VLSI Signal Processing 43(2-3): 247-258 (2006)
Jürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner, Topic 18: Embedded Parallel Systems., Euro-Par 2006: 1179
J. Chamorro-Martinez, D. Sanchez, B. Prados-Suarez, E. Galan-Perales, Fuzzy homogeneity measures for path-based colour image segmentation, International Journal of Intelligent Systems Technologies and Applications , Volume 1 Issue 3/4, Inderscience Publishers, June 2006
J. J. Costa, Toni Cortes, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Running OpenMP applications efficiently on an everything-shared SDSM., J. Parallel Distrib. Comput. 66(5): 647-658 (2006)
Jacob A. Bower, Wayne Luk, Oskar Mencer, Michael J. Flynn, Martin Morf, Dynamic clock-frequencies for FPGAs., Microprocessors and Microsystems 30(6): 388-397 (2006)
Jacqueline Chame, Chun Chen, Pedro C. Diniz, Mary W. Hall, Yoon-Ju Lee, Robert F. Lucas, An overview of the ECO project., IPDPS 2006
Jaeheon Jeong, Per Stenström, Michel Dubois, Simple penalty-sensitive replacement policies for caches., Conf. Computing Frontiers 2006: 341-352
JaeWoong Chung, Chi Cao Minh, Austen McDonald, Travis Skare, Hassan Chafi, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun, Tradeoffs in transactional memory virtualization., ASPLOS 2006: 371-381
JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun, The common case transactional behavior of multithreaded programs., HPCA 2006: 266-277
Jairo Balart, Marc González, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Runtime Address Space Computation for SDSM Systems., LCPC 2006: 330-344
Jamel Tayeb, Smaïl Niar, Adapting EPIC Architecture's Register Stack for Virtual Stack Machines., DSD 2006: 204-210
Jan Petzold, Faruk Bagci, Wolfgang Trumler, Theo Ungerer, Comparison of Different Methods for Next Location Prediction., Euro-Par 2006: 909-918
Jan Petzold, Faruk Bagci, Wolfgang Trumler, Theo Ungerer, Hybrid Predictors for Next Location Prediction., UIC 2006: 125-134
Jan-David Mol, Dick H. J. Epema, Henk J. Sips, The Orchard Algorithm: P2P Multicasting without Free-Riding., Peer-to-Peer Computing 2006: 275-282
Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe, Reunion: Complexity-Effective Multicore Redundancy., MICRO 2006: 223-234
Jari Heikkinen, Jarmo Takala, Effects of Program Compression., SAMOS 2006: 259-268
Jari K. Juntunen, Mauri Kuorilehto, Mikko Kohvakka, Ville Kaseva, Marko Hännikäinen, Timo D. Hämäläinen, WSN API: Application Programming Interface for Wireless Sensor Networks., PIMRC 2006: 1-5
Jari Nikara, Jarmo Takala, Jaakko Astola, Discrete cosine and sine transforms - regular algorithms and pipeline architectures., Signal Processing 86(2): 230-249 (2006)
Jarmo Takala, Konsta Punkka, Scalable FFT Processors and Pipelined Butterfly Units., VLSI Signal Processing 43(2-3): 113-123 (2006)
Jarno Vanne, Eero Aho, Timo Hämäläinen, Kimmo Kuusilinna, A High-Performance Sum of Absolute Difference Implementation for Motion Estimation., IEEE Trans. Circuits Syst. Video Techn. 16(7): 876-883 (2006)
Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, Babak Falsafi, Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays., IEEE Micro 26(1): 70-79 (2006)
Javier D. Bruguera, Roberto R. Osorio, A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization, DSD '06: Proceedings of the 9th EUROMICRO Conference on Digital System Design, IEEE Computer Society, August 2006
Javier D. Bruguera, Roberto R. Osorio, A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization., DSD 2006: 407-414
Javier Fernández, Félix García Carballeira, Jesús Carretero, Alejandro Calderón, José Daniel García, Disk Scheduling Proposal for an In-Band Bandwidth Virtualization Schema., PDPTA 2006: 669-675
Javier Garcia-Frias, Felipe Cabarcas, Approaching the Slepian-Wolf boundary using practical channel codes., Signal Processing 86(11): 3096-3101 (2006)
Javier Setoain, Christian Tenllado, Manuel Prieto, David Valencia, Antonio Plaza, Javier Plaza, Parallel Hyperspectral Image Processing on Commodity Graphics Hardware., ICPP Workshops 2006: 465-472
Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero, The impact of traffic aggregation on the memory performance of networking applications, Journal of Embedded Computing , Volume 2 Issue 1, IOS Press, January 2006
Jay L. T. Cornwall, Olav Beckmann, Paul H. J. Kelly, Automatically translating a general purpose C++ image processing library for GPUs., IPDPS 2006
Jehangir Khan, Yassin Elhillali, Smaïl Niar, Atika Rivenq, A Low Speed Digital Correlator Architecture Optimized For Resource Savings., ReCoSoC 2006: 207-213
Jeremy Gibbons, David Lester, Richard S. Bird, Functional Pearl: Enumerating the rationals., J. Funct. Program. 16(3): 281-291 (2006)
Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals, Software Demand Hardware Supply., IEEE Micro 26(4): 72-82 (2006)
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero, Speculative early register release., Conf. Computing Frontiers 2006: 291-302
Jesús Delicado, Luis Orozco-Barbosa, Francisco Delicado, Pedro Cuenca, A QoS-aware protocol architecture for WiMAX., CCECE 2006: 1779-1782
Jesús Labarta, Bernd Mohr, Allan Snavely, Jeffrey S. Vetter, Topic 2: Performance Prediction and Evaluation., Euro-Par 2006: 63
Jesus Alastruey, Jose Luis Briz, Pablo Ibanez, Victor Cinals, Software Demand, Hardware Supply, IEEE Micro , Volume 26 Issue 4, IEEE Computer Society Press, July 2006
Jeyarajan Thiyagalingam, Olav Beckmann, Paul H. J. Kelly, Is Morton layout competitive for large two-dimensional arrays yet?, Concurrency and Computation: Practice and Experience 18(11): 1509-1539 (2006)
Jia Guo, Ganesh Bikshandi, Daniel Hoeflinger, Gheorghe Almási, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Christoph von Praun, Hierarchically tiled arrays for parallelism and locality., IPDPS 2006
Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat Chakradhar, A design methodology for application-specific networks-on-chip, Transactions on Embedded Computing Systems (TECS) , Volume 5 Issue 2, ACM, May 2006
Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting., VLSI Signal Processing 43(2-3): 235-246 (2006)
Jie Tao, Siegfried Schloissnig, Wolfgang Karl, Analysis of the Spatial and Temporal Locality in Data Accesses., International Conference on Computational Science (2) 2006: 502-509
Jie Tao, Wolfgang Karl, Performance Evaluation of Adaptive Caching Schemes., ARCS Workshops 2006: 351-364
Jie Tao, Wolfgang Karl, Supporting Cache Locality Optimization with a Toolset., Euro-Par 2006: 25-34
Jie Tao, Wolfgang Karl, Detailed cache simulation for detecting bottleneck miss reason and optimization potentialities., VALUETOOLS 2006: 62
Jinfeng Huang, Jeroen Voeten, Henk Corporaal, Correctness-preserving synthesis for real-time control software., QSIC 2006: 65-73
Jinfeng Huang, Marc Geilen, Jeroen Voeten, Henk Corporaal, Branching-Time Property Preservation Between Real-Time Systems., ATVA 2006: 260-275
Jingling Xue, Jens Knoop, A Fresh Look at PRE as a Maximum Flow Problem., CC 2006: 139-154
Joachim Falk, Christian Haubelt, Jürgen Teich, Efficient Representation and Simulation of Model-Based Designs., FDL 2006: 129-135
Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata, Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA., FPL 2006: 1-4
Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata, SAD computation based on online arithmetic for motion estimation., Microprocessors and Microsystems 30(5): 250-258 (2006)
Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma, Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography., DATE 2006: 218-223
John Cavazos, Christophe Dubach, Felix V. Agakov, Edwin V. Bonilla, Michael F. P. O'Boyle, Grigori Fursin, Olivier Temam, Automatic performance model construction for the fast software exploration of new hardware designs., CASES 2006: 24-34
John Cavazos, J. Eliot B. Moss, Michael F. P. O'Boyle, Hybrid Optimizations: Which Optimization Algorithm to Use?., CC 2006: 124-138
John Cavazos, Michael F. P. O'Boyle, Method-specific dynamic compilation using logistic regression., OOPSLA 2006: 229-240
Jonas Maebe, Dries Buytaert, Lieven Eeckhout, Koen De Bosschere, Javana: a system for building customized Java program analysis tools., OOPSLA 2006: 153-168
Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung, Fast word-level power models for synthesis of FPGA-based arithmetic., ISCAS 2006
Jonathan Barre, Cédric Landet, Christine Rochange, Pascal Sainrat, Modeling Instruction-Level Parallelism for WCET Evaluation., RTCSA 2006: 61-67
Jorge García-Vidal, Maribel March, Llorenç Cerdà, Jesús Corbal, Mateo Valero, A DRAM/SRAM Memory Scheme for Fast Packet Buffers., IEEE Trans. Computers 55(5): 588-602 (2006)
José A. Gregorio, Bettina Schnor, Angelos Bilas, Olav Lysne, Topic 13: Routing and Communication in Interconnection Networks., Euro-Par 2006: 851
José Carlos Mouriño, María J. Martín, Patricia González, Ramon Doallo, Dynamic Load-Balancing for the STEM-II Air Quality Model., ICCSA (1) 2006: 701-710
José Carlos Mouriño, María J. Martín, Patricia González, Ramon Doallo, High Performance Air Quality Simulation in the European CrossGrid Project., Computers and Artificial Intelligence 25(4): (2006)
José Daniel García, Jesús Carretero, Félix García Carballeira, Javier Fernández, David E. Singh, Alejandro Calderón, Reliable Partial Replication of Contents in Web Clusters: Getting Storage without losing Reliability., JCP 1(7): 81-88 (2006)
José Daniel García, Jesús Carretero, Félix García, Javier Fernández, Alejandro Calderón, David E. Singh, A Quantitative Justification to Partial Replication of Web Contents., ICCSA (4) 2006: 1136-1145
José Daniel García, Jesús Carretero, Javier Fernández, Félix García, David E. Singh, Alejandro Calderón, On the Reliability of Web Clusters with Partial Replication of Contents., ARES 2006: 617-624
José Ignacio Aliaga, José M. Badía, Sergio Barrachina, Maribel Castillo, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Francisco Almeida, Vicente Bl, Parallelization of GSL: The Web Service Interface., PDP 2006: 301-307
José Luis Imaña, Juan Manuel Sánchez, Francisco Tirado, Bit-Parallel Finite Field Multipliers for Irreducible Trinomials., IEEE Trans. Computers 55(5): 520-533 (2006)
José Luis Imaña, Román Hermida, Francisco Tirado, Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials., IEEE Trans. VLSI Syst. 14(12): 1388-1393 (2006)
José Luis Martínez, Pedro Cuenca, Francisco Delicado, Luis Orozco-Barbosa, On the Capabilities of Quality Measures in Video Compresion Standards., CCECE 2006: 527-532
José M. Badía, Peter Benner, Rafael Mayo, Enrique S. Quintana-Ortí, Parallel Solution of Large-Scale and Sparse Generalized Algebraic Riccati Equations., Euro-Par 2006: 710-719
José Manuel Claver, Manel Canseco, P. Agustí, G. León, A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers., ISPA 2006: 86-97
José Miguel Montañana, Jose Flich, Antonio Robles, José Duato, Reachability-Based Fault-Tolerant Routing., ICPADS (1) 2006: 515-524
José Villalón, Pedro Cuenca, Luis Orozco-Barbosa, B-EDCA: A New IEEE 802.11e-Based QoS Protocol for Multimedia Wireless Communications., Networking 2006: 148-159
José Villalón, Pedro Cuenca, Luis Orozco-Barbosa, A Novel IEEE 802.11e-Based QoS Protocol for Voice Communications over WLANs., WWIC 2006: 224-235
José Villalón, Yongho Seok, Thierry Turletti, Pedro Cuenca, Luis Orozco-Barbosa, ARSM: Auto Rate Selection Multicast Mechanism for Multi-rate Wireless LANs., PWC 2006: 239-250
Jose Gonzalez-Mora, Nicolas Guil, Emilio L. Zapata, Tracking of Linear Appearance Models Using Second Order Minimization., ACIVS 2006: 1002-1013
Jose L. Ayala, David Atienza, Praveen Raghavan, Marisa Lopez-Vallejo, Francky Catthoor, Compilation for Delay Impact Minimization in VLIW Embedded Systems, IWIA '06: Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IEEE Computer Society, January 2006
Jose Maria Quintana, Maria Jose Avedillo, Hector Pettenghi, Self-Latching Operation Limits for MOBILE Circuits, Proc. Int. Symp. on Circuits and Syst., pp. 4579-4582
Jose Maria Quintana, Maria Jose Avedillo, Hector Pettenghi, Implementación de lógica umbral y multiumbral con RTDs, 12th IBERCHIP, no. 12
Josep Aguilar-Saborit, Pedro Trancoso, Victor Muntés-Mulero, Josep-Lluis Larriba-Pey, Dynamic count filters., SIGMOD Record 35(1): 26-32 (2006)
Josep Domènech, Ana Pont, Julio Sahuquillo, José A. Gil, Cost-Benefit Analysis of Web Prefetching Algorithms from the User's Point of View., Networking 2006: 1113-1118
Josep Domènech, José A. Gil, Julio Sahuquillo, Ana Pont, Web prefetching performance metrics: A survey., Perform. Eval. 63(9-10): 988-1004 (2006)
Josep Domènech, Julio Sahuquillo, Ana Pont, José A. Gil, Design keys to adapt web prefetching algorithms to environment conditions., COMSWARE 2006
Josep Domènech, Julio Sahuquillo, José A. Gil, Ana Pont, The Impact of the Web Prefetching Architecture on the Limits of Reducing User's Perceived Latency., Web Intelligence 2006: 740-744
Josep Jorba, Tomàs Margalef, Emilio Luque, Search of Performance Inefficiencies in Message Passing Applications with KappaPI 2 Tool., PARA 2006: 409-419
Josep L. Lérida, Francesc Solsona, Francesc Giné, Mauricio Hanzich, Porfidio Hernández, Emilio Luque, MetaLoRaS: A Predictable MetaScheduler for Non-dedicated Multiclusters., ISPA 2006: 630-641
Josep M. Pérez, Rosa M. Badia, Jesús Labarta, Including SMP in Grids as Execution Platform and Other Extensions in GRID Superscalar., e-Science 2006: 60
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin, Instruction packing: Toward fast and energy-efficient instruction scheduling., TACO 3(2): 156-181 (2006)
Joshua J. Yi, Hans Vandierendonck, Lieven Eeckhout, David J. Lilja, The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools., ICS 2006: 75-86
Joshua J. Yi, Lieven Eeckhout, David J. Lilja, Brad Calder, Lizy Kurian John, James E. Smith, The Future of Simulation: A Field of Dreams., IEEE Computer 39(11): 22-29 (2006)
Joshua J. Yi, Resit Sendag, Lieven Eeckhout, Ajay Joshi, David J. Lilja, Lizy Kurian John, Evaluating Benchmark Subsetting Approaches., IISWC 2006: 93-104
Juan C. Moure, Domingo Benitez, Dolores Rexachs, Emilio Luque, Wide and efficient trace prediction using the local trace predictor., ICS 2006: 55-65
Juan Carlos Pichel, David E. Singh, Francisco F. Rivera, Image segmentation based on merging of sub-optimal segmentations., Pattern Recognition Letters 27(10): 1105-1116 (2006)
Juan L. Aragón, José M. González, Antonio González, Control Speculation for Energy-Efficient Next-Generation Superscalar Processors., IEEE Trans. Computers 55(3): 281-291 (2006)
Juanjo Noguera, Rosa M. Badia, System-level power-performance tradeoffs for reconfigurable computing., IEEE Trans. VLSI Syst. 14(7): 730-739 (2006)
Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen, Design Implementation and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring., SAMOS 2006: 109-121
Julián Ramos Cózar, Nicolás Guil Mata, J. M. González-Linares, Emilio L. Zapata, Video Cataloging Based on Robust Logotype Detection., ICIP 2006: 3217-3220
Juraj Polakovic, Ali Erdem Özcan, Jean-Bernard Stefani, Building Reconfigurable Component-Based OS with THINK., EUROMICRO-SEAA 2006: 178-185
Jyrki Joutsensalo, Ari Viinikainen, Mika Wikström, Timo Hämäläinen, Bandwidth allocation and pricing in multimode network., AINA (1) 2006: 573-578
K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, A novel methodology for designing high-performance and low-energy FPGA routing architecture., FPGA 2006: 224
Karine Heydemann, François Bodin, Peter M. W. Knijnenburg, Laurent Morin, UFS: a global trade-off strategy for loop unrolling for VLIW architectures., Concurrency and Computation: Practice and Experience 18(11): 1413-1434 (2006)
Kenneth Hoste, Aashish Phansalkar, Lieven Eeckhout, Andy Georges, Lizy Kurian John, Koen De Bosschere, Performance prediction based on inherent program similarity., PACT 2006: 114-122
Kenneth Hoste, Lieven Eeckhout, Comparing Benchmarks Using Key Microarchitecture-Independent Characteristics., IISWC 2006: 83-92
Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini, Energy-Efficient Value Based Selective Refresh for Embedded DRAMS., J. Low Power Electronics 2(1): 70-79 (2006)
Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino, STV-Cache: a leakage energy-efficient architecture for data caches., ACM Great Lakes Symposium on VLSI 2006: 404-409
Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino, Reducing Conflict Misses by Application-Specific Reconfigurable Indexing., IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2626-2637 (2006)
Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Memory Access Micro-Profiling for ASIP Design., DELTA 2006: 255-262
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia, Design and implementation of a modular and portable IEEE 754 compliant floating-point unit., DATE Designers' Forum 2006: 221-226
Klaus Danne, Marco Platzner, Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware., IPDPS 2006
Klaus Danne, Marco Platzner, An EDF schedulability test for periodic tasks on reconfigurable hardware devices., LCTES 2006: 93-102
Klaus Danne, Roland Muhlenbernd, Marco Platzner, Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions., FPL 2006: 1-6
Koen Bertels, João M. P. Cardoso, Stamatis Vassiliadis, Reconfigurable Computing: Architectures and Applications Second International Workshop ARC 2006 Delft The Netherlands March 1-3 2006 Revised Selected Papers, Springer 2006
Konstantinos Xinidis, Ioannis Charitakis, Spyros Antonatos, Kostas G. Anagnostakis, Evangelos P. Markatos, An Active Splitter Architecture for Intrusion Detection and Prevention., IEEE Trans. Dependable Sec. Comput. 3(1): 31-44 (2006)
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope, Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors., Comput. J. 49(2): 211-233 (2006)
Kostas Siozios, Dimitrios Soudris, Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures., FPL 2006: 1-4
Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis, A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications., ISCAS 2006
Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis, Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources., PATMOS 2006: 403-414
Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis, Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique., VLSI-SoC 2006: 204-209
Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis, Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications., IPDPS 2006
Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Koen De Bosschere, Wilfried Philips, Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture., ARC 2006: 52-58
Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, Space-Efficient 64-bit Java Objects through Selective Typed Virtual Addressing., CGO 2006: 76-86
Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, 64-bit versus 32-bit Virtual Machines for Java., Softw. Pract. Exper. 36(1): 1-26 (2006)
Krisztián Flautner, Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems., CODES+ISSS 2006: 265
Kyriakos Stavrou, Pedro Trancoso, Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems., DSD 2006: 123-126
Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou, Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor., Asia-Pacific Computer Systems Architecture Conference 2006: 244-259
L. M. Sánchez García, Florin Isaila, Félix García Carballeira, Jesús Carretero Pérez, Rolf Rabenseifner, Panagiotis A. Adamidis, A New I/O Architecture for Improving the Performance in Large Scale Clusters., ICCSA (5) 2006: 108-117
Laila Sakkila, P. Deloof, Yassin Elhillali, Atika Rivenq, Smaïl Niar, A Real Time Signal Processing for an Anticollision Road Radar System., VTC Fall 2006: 1-5
Lari Kannisto, Ari Viinikainen, Jyrki Joutsensalo, Timo Hämäläinen, Adaptive Algorithm for Revenue Maximization in WFQ Scheduler., AINA (1) 2006: 339-346
Lars Wehmeyer, Peter Marwedel, Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation, Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation, Springer-Verlag New York, Inc., August 2006
Laura Pozzi, Kubilay Atasu, Paolo Ienne, Exact and approximate algorithms for the extension of embedded processor instruction sets., IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1209-1229 (2006)
Laurence Tianruo Yang, Hai Jin, Jianhua Ma, Theo Ungerer, Autonomic and Trusted Computing Third International Conference ATC 2006 Wuhan China September 3-6 2006 Proceedings, Springer 2006
Leandro Souza, Ana Ripoll, Xiaoyuan Yang, Emilio Luque, Fernando Cores, On the Relevance of Network Topologies in Distributed Video-on-Demand Servers., PDP 2006: 396-404
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, FPGAs GPUs and the PS2 - A Single Programming Methodology., FCCM 2006: 313-314
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, Oliver Pell, Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description., FPL 2006: 1-6
Lei Gao, Yongsheng Ding, Hao Ying, Economics-inspired decentralized control approach for adaptive grid services and applications., Int. J. Intell. Syst. 21(12): 1269-1288 (2006)
Lieven Eeckhout, Koen De Bosschere, Yet shorter warmup by combining no-state-loss and MRRL for sampled LRU cache simulation., Journal of Systems and Software 79(5): 645-652 (2006)
Liliana Cucu, Joël Goossens, Feasibility Intervals for Fixed-Priority Real-Time Scheduling on Uniform Multiprocessors., ETFA 2006: 397-404
Liping Xue, Ozcan Ozturk, Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu, Dynamic partitioning of processing and memory resources in embedded MPSoC architectures., DATE 2006: 690-695
Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis, A reconfigurable hardware based embedded scheduler for buffered crossbar switches., FPGA 2006: 143-149
Lotfi Mhamdi, Mounir Hamdi, Christopher Kachris, Stephan Wong, Stamatis Vassiliadis, High-performance switching based on buffered crossbar fabrics., Computer Networks 50(13): 2271-2285 (2006)
Luca Benini, Application specific NoC design., DATE 2006: 491-495
Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano, Allocation Scheduling and Voltage Scaling on Energy Aware MPSoCs., CPAIOR 2006: 44-58
Luca Benini, Elisabetta Farella, Carlotta Guiducci, Wireless sensor networks: Enabling technology for ambient intelligence., Microelectronics Journal 37(12): 1639-1649 (2006)
Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, ASIP design and synthesis for non linear filtering in image processing., DATE Designers' Forum 2006: 233-238
Luca Fanucci, Pasquale Ciao, Giulio Colavolpe, VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes., IEICE Transactions 89-A(7): 1976-1986 (2006)
Ludo Van Put, Bjorn De Sutter, Matias Madou, Bruno De Bus, Dominique Chanet, Kristof Smits, Koen De Bosschere, LANCET: a nifty code editing tool, PASTE '05: Proceedings of the 6th ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering, ACM, January 2006
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Victor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity, MEDEA '06: Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, ACM, September 2006
Luis Miguel Sánchez, Florin Isaila, Alejandro Calderón, David E. Singh, José Daniel García, Improving the Performance of Cluster Applications through I/O Proxy Architecture., CLUSTER 2006
Luk Van Ertvelde, Filip Hellebaut, Lieven Eeckhout, Koen De Bosschere, NSL-BLRL: Efficient CacheWarmup for Sampled Processor Simulation., Annual Simulation Symposium 2006: 168-177
M. Aldea, Guillem Bernat, Ian Broster, Alan Burns, Radu Dobrin, José M. Drake, Gerhard Fohler, Paolo Gai, Michael González Harbour, Giacomo Guidi, J. Javier Gutiérrez, Tomas Lennv, FSF: A Real-Time Scheduling Architecture Framework., IEEE Real Time Technology and Applications Symposium 2006: 113-124
M. Anton Ertl, Kevin Casey, David Gregg, Fast and flexible instruction selection with on-demand tree-parsing automata., PLDI 2006: 52-60
M. Goyeneche, Jesús E. Villadangos, José Javier Astrain, Manuel Prieto, Alberto Córdoba, A distributed data gathering algorithm for wireless sensor networks with uniform architecture., PE-WASUN 2006: 162-166
M.E.Castro, Roberto R. Osorio, Javier D. Bruguera, Optimizing CABAC for VLIW architectures, Proc. XXI Conference on Design of Circuits and Integrated Systems (DCIS2006)
Manish Verma, Lars Wehmeyer, Peter Marwedel, Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems., IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2035-2051 (2006)
Manish Verma, Lars Wehmeyer, Robert Pyka, Peter Marwedel, Luca Benini, Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations ., SAMOS 2006: 279-288
Manish Verma, Peter Marwedel, Overlay techniques for scratchpad memories in low power embedded processors., IEEE Trans. VLSI Syst. 14(8): 802-815 (2006)
Manolis Marazakis, Konstantinos Xinidis, Vassilis Papaefstathiou, Angelos Bilas, Efficient remote block-level I/O over an RDMA-capable NIC., ICS 2006: 97-106
Manolis Marazakis, Vassilis Papaefstathiou, Giorgos Kalokairinos, Angelos Bilas, Experiences from Debugging a PCIX-based RDMA-capable NIC., CLUSTER 2006
Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren, Retargetable code optimization with SIMD instructions., CODES+ISSS 2006: 148-153
Manuel Prieto, Jesús E. Villadangos, Federico Fariña, Alberto Córdoba, An O(n) Distributed Deadlock Resolution Algorithm., PDP 2006: 48-55
María Blanca Ibáñez, Félix García, Jesús Carretero, A Profiling Approach for the Management of Writing in Irregular Applications., ISPA Workshops 2006: 251-259
María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida, Bitwise scheduling to balance the computational cost of behavioral specifications., IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 31-46 (2006)
María Cruz Valiente, Gonzalo Génova, Jesús Carretero, UML 2.0 Notation for Modeling Real Time Task Scheduling., Journal of Object Technology 5(4): 91-105 (2006)
María Engracia Gómez, Nils Agne Nordbotten, Jose Flich, Pedro López, Antonio Robles, José Duato, Tor Skeie, Olav Lysne, A Routing Methodology for Achieving Fault Tolerance in Direct Networks., IEEE Trans. Computers 55(4): 400-415 (2006)
María Engracia Gómez, Pedro López, José Duato, FIR: An efficient routing strategy for tori and meshes., J. Parallel Distrib. Comput. 66(7): 907-921 (2006)
María S. Pérez, Jesús Carretero, Félix García Carballeira, José Manuel Peña, Víctor Robles, MAPFS: A flexible multiagent parallel file system for clusters., Future Generation Comp. Syst. 22(5): 620-632 (2006)
Marc Duranton, The Challenges for High Performance Embedded Systems., DSD 2006: 3-7
Marcel D. van de Burgwal, Gerard J. M. Smit, Gerard K. Rauwerda, Paul M. Heysters, Hydra: An Energy-efficient and Reconfigurable Network Interface., ERSA 2006: 171-177
Marco Aldinucci, Marco Danelutto, Marco Vanneschi, Autonomic QoS in ASSIST Grid-Aware Components., PDP 2006: 221-230
Marco D. Santambrogio, Donatella Sciuto, Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign., FPL 2006: 1-2
Marco Danelutto, Marco Aldinucci, Algorithmic skeletons meeting grids., Parallel Computing 32(7-8): 449-462 (2006)
Marco Giorgetta, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini, A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures., VLSI-SoC 2006: 24-29
Marek Wieczorek, Mumtaz Siddiqui, Alex Villazón, Radu Prodan, Thomas Fahringer, Applying Advance Reservation to Increase Predictability of Workflow Execution on the Grid., e-Science 2006: 82
Marek Wieczorek, Radu Prodan, Thomas Fahringer, Dynamic Programming Based Approach for Bi-criteria Workflow Scheduling on the Grid., HPDC 2006: 381-382
Margarita Amor, Montserrat Bóo, Emilio J. Padrón, Dirk Bartz, Hardware Oriented Algorithms for Rendering Order-Independent Transparency., Comput. J. 49(2): 201-210 (2006)
Maria Jose Avedillo, Jose Maria Quintana, Hector Pettenghi, Self-Latching Operation of MOBILE Circuits using Series-Connection of RTDs and Transistors, EEE Trans. on Circuits and Systems II, vol. 53, no. 5, pp. 334-338
Maria Jose Avedillo, Jose Maria Quintana, Hector Pettenghi, Increased Logic Functionality of Clocked Series-Connected RTDs, IEEE Trans. on Nanotechnology, vol. 5, no. 5, pp. 606- 611
Marina Alonso, Salvador Coll, Juan Miguel Martínez, Vicente Santonja, Pedro López, José Duato, Dynamic power saving in fat-tree interconnection networks using on/off links., IPDPS 2006
Marius Mikalsen, Jacqueline Floch, Nearchos Paspallis, George A. Papadopoulos, Pedro Antonio Ruiz, Putting Context in Context: The Role and Design of Context Management in a Mobility and Adaptation Enabling Middleware, MDM '06: Proceedings of the 7th International Conference on Mobile Data Management (MDM'06) - Volume 00 , Volume 00, IEEE Computer Society, May 2006
Marius Mikalsen, Nearchos Paspallis, Jacqueline Floch, Erlend Stav, George A. Papadopoulos, Akis Chimaris, Distributed context management in a mobility and adaptation enabling middleware (MADAM), SAC '06: Proceedings of the 2006 ACM symposium on Applied computing, ACM, April 2006
Mark Silberstein, Dan Geiger, Assaf Schuster, A Distributed System for Genetic Linkage Analysis., GCCB 2006: 110-123
Mark Silberstein, Dan Geiger, Assaf Schuster, Miron Livny, Scheduling Mixed Workloads in Multi-grids: The Grid Execution Hierarchy., HPDC 2006: 291-302
Mark Silberstein, Gabriel Kliot, Artyom Sharov, Assaf Schuster, Miron Livny, Materializing Highly Available Grids., HPDC 2006: 321-323
Mark Thompson, Andy D. Pimentel, Simon Polstra, Cagkan Erbas, A Mixed-level Co-simulation Method for System-level Design Space Exploration., ESTImedia 2006: 27-32
Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli, A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control., CODES+ISSS 2006: 130-135
Martin Brain, Tom Crick, Marina De Vos, John Fitch, TOAST: Applying Answer Set Programming to Superoptimisation., ICLP 2006: 270-284
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Symbolic Archive Representation for a Fast Nondominance Test., EMO 2006: 111-125
Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor, Systematic Preprocessing of Data Dependent Constructs for Embedded Systems., J. Low Power Electronics 2(1): 9-1 (2006)
Martin Streubühr, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf, Task-accurate performance modeling in SystemC for real-time multi-processor architectures., DATE 2006: 480-481
Martin Thuresson, Per Stenström, Scalable Value-Cache Based Compression Schemes for Multiprocessors., SBAC-PAD 2006: 117-124
Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano, Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip., DATE 2006: 3-8
Mary Jane Irwin, Koen De Bosschere, Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages Compilers and Tools for Embedded Systems (LCTES'06) Ottawa Ontario Canada June 14-16 2006, ACM 2006
Massimo Rovini, Francesco Rossi, Pasquale Ciao, Nicola L'Insalat, Luca Fanucci, Layered Decoding of Non-Layered LDPC Codes., DSD 2006: 537-544
Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich, A Flexible Reconfiguration Manager for the Erlangen Slot Machine., ARCS Workshops 2006: 183-194
Mathias Pacher, Alexander von Renteln, Uwe Brinkschulte, Towards an Organic Middleware for Real-Time Applications., ISORC 2006: 400-407
Matias Madou, Bertrand Anckaert, Bruno De Bus, Koen De Bosschere, Jan Cappaert, Bart Preneel, On the Effectiveness of Source Code Transformations for Binary Obfuscation., Software Engineering Research and Practice 2006: 527-533
Matias Madou, Ludo Van Put, Koen De Bosschere, Understanding Obfuscated Code., ICPC 2006: 268-274
Matias Madou, Ludo Van Put, Koen De Bosschere, LOCO: an interactive code (De)obfuscation tool., PEPM 2006: 140-144
Mats Brorsson, Mikael Collin, Adaptive and flexible dictionary code compression for embedded applications., CASES 2006: 113-124
Mats Brorsson, Mikael Collin, Adaptive and flexible dictionary code compression for embedded applications, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, Power/performance hardware optimization for synchronization intensive applications in MPSoCs., DATE 2006: 606-611
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors., ICSAMOS 2006: 144-151
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, Efficient Synchronization for Embedded On-Chip Multiprocessors., IEEE Trans. VLSI Syst. 14(10): 1049-1062 (2006)
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, An efficient synchronization technique for multiprocessor systems on-chip, MEDEA '05: Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture, ACM, March 2006
Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow., VLSI-SoC 2006: 74-79
Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Christos D. Antonopoulos, PACMAN: A PerformAnce Counters MANager for Intel Hyperthreaded Processors., QEST 2006: 141-144
Matthew Curtis-Maury, James Dzierwa, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Online power-performance adaptation of multithreaded programs using hardware event-based prediction., ICS 2006: 157-166
Matthew Curtis-Maury, James Dzierwa, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Online strategies for high-performance power-aware thread execution on emerging multiprocessors., IPDPS 2006
Mauricio Alvarez, Ricardo Henao, Probabilistic Kernel Principal Component Analysis Through Time., ICONIP (1) 2006: 747-754
Mauricio Hanzich, Josep L. Lérida, Matías Torchinsky, Francesc Giné, Porfidio Hernández, Emilio Luque, Using On-the-Fly Simulation for Estimating the Turnaround Time on Non-dedicated Clusters., Euro-Par 2006: 177-187
Mauricio Hanzich, Porfidio Hernández, Emilio Luque, Francesc Giné, Francesc Solsona, Josep L. Lérida, Using Simulation Historical and Hybrid Estimation Systems for Enhacing Job Scheduling on NOWs., CLUSTER 2006
Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania, A methodology for design of application specific deadlock-free routing algorithms for NoC systems., CODES+ISSS 2006: 142-147
Maurizio Palesi, Shashi Kumar, Rickard Holsmark, A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures., SAMOS 2006: 373-384
Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto, Combined software and hardware techniques for the design of reliable IP processors., DFT 2006: 265-273
Md. Mafijul Islam, Per Stenström, Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations., ICSAMOS 2006: 28-34
Melanie R. Rieback, Georgi Gaydadjiev, Bruno Crispo, Rutger F. H. Hofman, Andrew S. Tanenbaum, A Platform for RFID Security and Privacy Administration (Awarded Best Paper!)., LISA 2006: 89-102
Mercedes Marqués, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Specialized Spectral Division Algorithms for Generalized Eigenproblems Via the Inverse-Free Iteration., PARA 2006: 157-166
Michael Bender, Dror G. Feitelson, Allan Gottlieb, Uwe Schwiegelshohn, Topic 3: Scheduling and Load Balancing., Euro-Par 2006: 155
Michael Factor, Assaf Schuster, Konstantin Shagin, A Platform-Independent Distributed Runtime for Standard Multithreaded Java., International Journal of Parallel Programming 34(2): 113-142 (2006)
Michael Van Biesbrouck, Brad Calder, Lieven Eeckhout, Efficient Sampling Startup for SimPoint., IEEE Micro 26(4): 32-42 (2006)
Michael Van Biesbrouck, Lieven Eeckhout, Brad Calder, Considering all starting points for simultaneous multithreading simulation., ISPASS 2006: 143-153
Michail Flouris, Renaud Lachaize, Angelos Bilas, Using Lightweight Transactions and Snapshots for Fault-Tolerant Services Based on Shared Storage Bricks., CLUSTER 2006
Michail Papamichail, Dimitris Karadimas, Kostas Efstathiou, George Papadopoulos, Linear range extension of a phase-frequency-detector with saturated output., ISCAS 2006
Michalis Polychronakis, Kostas G. Anagnostakis, Evangelos P. Markatos, Network-Level Polymorphic Shellcode Detection Using Emulation., DIMVA 2006: 54-73
Michele Sama, Vincenzo Pacella, Elisabetta Farella, Luca Benini, Bruno Riccò, 3dID: a low-power low-cost hand motion capture device., DATE Designers' Forum 2006: 136-141
Michiel D'Haene, Benjamin Schrauwen, Dirk Stroobandt, Accelerating Event Based Simulation for Multi-synapse Spiking Neural Networks., ICANN (1) 2006: 760-769
Mikko Kohvakka, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen, Transmission Power Based Path Loss Metering for Wireless Sensor Networks., PIMRC 2006: 1-5
Mikko Kohvakka, Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen, Performance analysis of IEEE 802.15.4 and ZigBee for large-scale wireless sensor network applications., PE-WASUN 2006: 48-57
Mikko Kohvakka, Tero Arpinen, Marko Hännikäinen, Timo D. Hämäläinen, High-performance multi-radio WSN platform, REALMAN '06: Proceedings of the 2nd international workshop on Multi-hop ad hoc networks: from theory to reality, ACM, May 2006
Mikko Setälä, Petri Kukkala, Tero Arpinen, Marko Hännikäinen, Timo D. Hämäläinen, Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform., SAMOS 2006: 27-38
Mila Dalla Preda, Matias Madou, Koen De Bosschere, Roberto Giacobazzi, Opaque Predicates Detection by Abstract Interpretation., AMAST 2006: 81-95
Milan Tichý, Andy Nisbet, David Gregg, GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems., FPGA 2006: 236
Milan Tichý, Jan Schier, David Gregg, Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA., ARC 2006: 311-316
Miljan Vuletic, Laura Pozzi, Paolo Ienne, Virtual memory window for application-specific reconfigurable coprocessors., IEEE Trans. VLSI Syst. 14(8): 910-915 (2006)
Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis, A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck., IEEE Trans. VLSI Syst. 14(3): 279-291 (2006)
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson, Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration., ISQED 2006: 557-563
Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero, A decoupled KILO-instruction processor., HPCA 2006: 53-64
Mirko Loghi, Massimo Poncino, Luca Benini, Synchronization-driven dynamic speed scaling for MPSoCs., ISLPED 2006: 346-349
Mirko Loghi, Massimo Poncino, Luca Benini, Cache coherence tradeoffs in shared-memory MPSoCs., ACM Trans. Embedded Comput. Syst. 5(2): 383-407 (2006)
Mladen Berekovic, Tim Niggemeier, A Scalable Multi-thread Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme., SAMOS 2006: 289-298
Mohammad Abdullah Al Faruque, Gereon Weiss, Joerg Henkel, Bounded arbitration algorithm for QoS-supported on-chip communication, CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, ACM, October 2006
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto, Single-Event Upset Analysis and Protection in High Speed Circuits., European Test Symposium 2006: 29-34
Montse Farreras, Toni Cortes, Jesús Labarta, George Almási, Scaling MPI to short-memory MPPs such as BG/L., ICS 2006: 209-218
Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee, Efficient System-on-Chip Energy Management with a Segmented Bloom Filter., ARCS 2006: 283-297
Mumtaz Siddiqui, Alex Villazón, Thomas Fahringer, Grid allocation and reservation - Grid capacity planning with negotiation-based advance reservation for optimized QoS., SC 2006: 103
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, On-Chip Communication in Run-Time Assembled Reconfigurable Systems., ICSAMOS 2006: 168-176
Nabil Hasasneh, Ian Bell, Chris R. Jesshope, Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors., ARCS 2006: 252-267
Nalini Moti Belaramani, Michael Dahlin, Lei Gao, Amol Nayate, Arun Venkataramani, Praveen Yalagandula, Jiandan Zheng, PRACTI Replication., NSDI 2006
Nastaran Baradaran, Pedro C. Diniz, Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures., FPL 2006: 1-6
Nathan Clark, Amir Hormati, Scott A. Mahlke, Sami Yehia, Scalable subgraph mapping for acyclic computation accelerators., CASES 2006: 147-157
Nearchos Paspallis, George A. Papadopoulos, An Approach for Developing Adaptive, Mobile Applications with Separation of Concerns, COMPSAC '06: Proceedings of the 30th Annual International Computer Software and Applications Conference (COMPSAC'06) - Volume 01 , Volume 01, IEEE Computer Society, September 2006
Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko, Yield enhancements of design-specific FPGAs., FPGA 2006: 93-100
Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko, Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs., FPL 2006: 1-6
Nicolas Vasilache, Cédric Bastoul, Albert Cohen, Polyhedral Code Generation in the Real World., CC 2006: 185-201
Nicolas Vasilache, Cédric Bastoul, Albert Cohen, Sylvain Girbal, Violated dependence analysis., ICS 2006: 335-344
Nikolaos Chrysos, Manolis Katevenis, Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics., INFOCOM 2006
Nikolaos Drosinos, Georgios I. Goumas, Nectarios Koziris, Selecting the tile shape to reduce the total communication volume., IPDPS 2006
Nikolaos Drosinos, Nectarios Koziris, The Effect of Process Topology and Load Balancing on Parallel Programming Models for SMP Clusters and Iterative Algorithms., The Journal of Supercomputing 35(1): 65-91 (2006)
Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis, Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors., VLSI Signal Processing 44(1-2): 153-171 (2006)
Nikolas Kroupis, Stylianos Mamagkakis, Dimitrios Soudris, An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems., ESTImedia 2006: 21-26
Noam Palatin, Arie Leizarowitz, Assaf Schuster, Ran Wolff, Mining for misconfigured machines in grid systems., KDD 2006: 687-692
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh, High-level power analysis for multi-core chips., CASES 2006: 389-400
Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod, Dynamic Voltage Scaling Aware Delay Fault Testing., European Test Symposium 2006: 15-20
Norbert Wehn, Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems., ISVLSI 2006: 3
Norbert Wehn, Timo Vogt, Christian Neeb, A Reconfigurable Outer Modem Platform for Future Communications Systems., Dynamically Reconfigurable Architectures 2006
Oana Florescu, Jeroen Voeten, Marcel Verhoef, Henk Corporaal, Reusing Real-Time Systems Design Experience., FDL 2006: 375-381
Oana Florescu, Jinfeng Huang, Jeroen Voeten, Henk Corporaal, Strengthening Property Preservation in Concurrent Real-Time Systems., RTCSA 2006: 106-109
Oana Florescu, Menno de Hoon, Jeroen Voeten, Henk Corporaal, Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems., SAMOS 2006: 206-215
Oguz Ergin, Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors., PATMOS 2006: 477-485
Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose, Early Register Deallocation Mechanisms Using Checkpointed Register Files., IEEE Trans. Computers 55(9): 1153-1166 (2006)
Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González, Exploiting Narrow Values for Soft Error Tolerance., Computer Architecture Letters 5(2): (2006)
Olav Lysne, Tor Skeie, Sven-Arne Reinemo, Ingebjørg Theiss, Layered Routing in Irregular Networks., IEEE Trans. Parallel Distrib. Syst. 17(1): 51-65 (2006)
Oliver Pell, Wayne Luk, Generating Parametrised Hardware Libraries from Higher-Order Descriptions., FCCM 2006: 297-298
Oliver Pell, Wayne Luk, Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information., FPL 2006: 1-6
Oliver Sinnen, Leonel Augusto Sousa, Frode Eika Sandnes, Toward a Realistic Task Scheduling Model., IEEE Trans. Parallel Distrib. Syst. 17(3): 263-275 (2006)
Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero, Branch predictor guided instruction decoding., PACT 2006: 202-211
Olivier Rochecouste, Gilles Pokam, André Seznec, A case for a complexity-effective width-partitioned microarchitecture., TACO 3(3): 295-326 (2006)
Olli Alanen, Timo Hämäläinen, Eero Wallenius, Network and System Performance Management for Next Generation Networks., AINA (1) 2006: 689-692
Orna Grumberg, Tamir Heyman, Assaf Schuster, A work-efficient distributed algorithm for reachability analysis., Formal Methods in System Design 29(2): 157-175 (2006)
Osman S. Unsal, James Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin, Impact of Parameter Variations on Circuits and Microarchitecture., IEEE Micro 26(6): 30-39 (2006)
Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio González, Empowering a helper cluster through data-width aware instruction selection policies., IPDPS 2006
Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser, Safe Design Methodology for an Intelligent Cruise Control System with GPS., VTC Fall 2006: 1-5
Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser, Pierre Boulet, UML2 Profile for Modeling Controlled Data Parallel Applications., FDL 2006: 359-367
Owen Callanan, David Gregg, Andy Nisbet, Mike Peardon, High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD., FPL 2006: 1-6
Ozcan Ozturk, Feng Wang, Mahmut T. Kandemir, Yuan Xie, Optimal topology exploration for application-specific 3D architectures., ASP-DAC 2006: 390-395
Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy, Cache miss clustering for banked memory systems., ICCAD 2006: 244-250
Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy, An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors., ISVLSI 2006: 50-58
Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Multi-compilation: capturing interactions among concurrently-executing applications., Conf. Computing Frontiers 2006: 157-170
Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu, Compiler-Guided data compression for reducing memory consumption of embedded applications., ASP-DAC 2006: 814-819
Ozcan Ozturk, Guilin Chen, Mahmut T. Kandemir, Optimizing code parallelization through a constraint network based approach., DAC 2006: 863-688
Ozcan Ozturk, Mahmut T. Kandemir, Data Replication in Banked DRAMs for Reducing Energy Consumption., ISQED 2006: 551-556
Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu, Shared Scratch-Pad Memory Space Management., ISQED 2006: 576-584
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun, Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors., ICPADS (1) 2006: 383-390
Ozcan Ozturk, Mahmut T. Kandemir, Seung Woo Son, Mustafa Karaköy, Selective code/data migration for reducing communication energy in embedded MpSoC architectures., ACM Great Lakes Symposium on VLSI 2006: 386-391
Ozcan Ozturk, Mahmut T. Kandemir, Suleyman Tosun, An ILP based approach to address code generation for digital signal processors., ACM Great Lakes Symposium on VLSI 2006: 37-42
P. Marwedel, Embedded System Design, Embedded System Design, Springer-Verlag New York, Inc., March 2006
Pablo Garcia Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli, A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework., VLSI-SoC 2006: 140-145
Panagiota Fatourou, Faith Ellen Fich, Eric Ruppert, Time-space tradeoffs for implementations of snapshots., STOC 2006: 169-178
Panagiota Fatourou, Nikolaos D. Kallimanis, Single-scanner multi-writer snapshot implementations are fast!, PODC 2006: 228-237
Panos Trimintzios, Michalis Polychronakis, Antonis Papadogiannakis, Michalis Foukarakis, Evangelos P. Markatos, Arne Øslebø, DiMAPI: An Application Programming Interface for Distributed Network Monitoring., NOMS 2006: 382-393
Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen, Riku Soininen, Risto Rautee, Design and implementation of real-time betting system with offline terminals., Electronic Commerce Research and Applications 5(2): 170-188 (2006)
Panu Hämäläinen, Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen, Security in Wireless Sensor Networks: Considerations and Experiments., SAMOS 2006: 167-177
Panu Hämäläinen, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen, Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core., DSD 2006: 577-583
Paolo Ienne, Rainer Leupers, Customizable Embedded Processors: Design Technologies and Applications (Systems on Silicon), CustomizableEmbedded Processors: Design Technologies and Applications (Systems on Silicon), Morgan Kaufmann Publishers Inc., July 2006
Paraskevas Evripidou, George Samaras, Metacomputing with Mobile Agents., International Journal of Parallel Programming 34(5): 429-458 (2006)
Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi, Automatic identification of application-specific functional units with architecturally visible storage., DATE 2006: 212-217
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne, ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors., IEEE Trans. VLSI Syst. 14(7): 754-762 (2006)
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi, Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core., VLSI Design 2006: 651-656
Paul Feautrier, Scalable and Structured Scheduling., International Journal of Parallel Programming 34(5): 459-487 (2006)
Paul M. Heysters, The Era of Reconfigurable Computing., ERSA 2006: 257-264
Paul M. Heysters, Coarse-Grained Reconfigurable Computing for Power Aware Applications., ERSA 2006: 272-
Paula Cecilia Fritzsche, Concepció Roig, Ana Ripoll, Emilio Luque, Aura Hernandez, A Performance Prediction Methodology for Data-dependent Parallel Applications., CLUSTER 2006
Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten, Modeling Cache Sharing on Chip Multiprocessor Architectures., IISWC 2006: 160-171
Pedro C. Diniz, Gokul Govindu, Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit., FPL 2006: 1-4
Pedro Carmona-Saez, Roberto D. Pascual-Marqui, Francisco Tirado, José María Carazo, Alberto D. Pascual-Montano, Biclustering of gene expression data by non-smooth non-negative matrix factorization., BMC Bioinformatics 7: 78 (2006)
Pedro Cuenca, Luis Orozco-Barbosa, Personal Wireless Communications IFIP TC6 11th International Conference PWC 2006 Albacete Spain September 20-22 2006 Proceedings, Springer 2006
Pedro Javier García, Francisco J. Quiles, Jose Flich, José Duato, Ian Johnson, Finbar Naven, RECN-DD: A Memory-Efficient Congestion Management Technique for Advanced Switching., ICPP 2006: 23-32
Pedro Javier García, Francisco J. Quiles, Jose Flich, José Duato, Ian Johnson, Finbar Naven, Efficient Scalable Congestion Management for Interconnection Networks., IEEE Micro 26(5): 52-66 (2006)
Pedro Morillo, Juan M. Orduña, José Duato, A Scalable Synchronization Technique for Distributed Virtual Environments Based on Networked-Server Architectures., ICPP Workshops 2006: 74-81
Pedro Morillo, Juan M. Orduña, Marcos Fernández, Workload Characterization in Multiplayer Online Games., ICCSA (1) 2006: 490-499
Pedro Morillo, W. Moncho, Juan M. Orduña, José Duato, Providing Full Awareness to Distributed Virtual Environments Based on Peer-to-Peer Architectures., Computer Graphics International 2006: 336-347
Pedro Trancoso, Adaptive High-End Microprocessor for Power-Performance Efficiency., DSD 2006: 221-228
Pedro Trancoso, Paraskevas Evripidou, Kyriakos Stavrou, Costas Kyriacou, A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model., International Journal of Parallel Programming 34(3): 213-235 (2006)
Pepijn J. de Langen, Ben H. H. Juurlink, Leakage-aware multiprocessor scheduling for low power., IPDPS 2006
Per Stenström, Chip-multiprocessing and beyond., HPCA 2006: 109
Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala, Software Pipelining Support for Transport Triggered Architecture Processors., SAMOS 2006: 237-247
Peter Benner, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Solving Stable Sylvester Equations via Rational Iterative Schemes., J. Sci. Comput. 28(1): 51-83 (2006)
Peter Brunner, Hong Linh Truong, Thomas Fahringer, Performance Monitoring and Visualization of Grid Scientific Workflows in ASKALON., HPCC 2006: 170-179
Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich, Dynamically Reconfigurable Architectures 02.04. - 07.04.2006, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI) Schloss Dagstuhl Germany 2006
Petra Povalej, Mateja Verlic, Peter Kokol, José L. Sánchez, Jose F. Sigut, Identifying Lymphoma in Microscopy Images with Classificational Cellular Automata., CBMS 2006: 309-314
Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen, Configurable Protocol Engine for Runtime-Configurable Communication Subsystems on Multiprocessor SoC., PIMRC 2006: 1-5
Petros Oikonomakos, Mark Zwolinski, On the Design of Self-Checking Controllers with Datapath Interactions., IEEE Trans. Computers 55(11): 1423-1434 (2006)
Petros Oikonomakos, Mark Zwolinski, An Integrated High-Level On-Line Test Synthesis Tool., IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2479-2491 (2006)
Philippe Clauss, Bénédicte Kenmei, Polyhedral Modeling and Analysis of Memory Access Profiles., ASAP 2006: 191-198
Philippe Faes, Bram Minnaert, Mark Christiaens, Eric Bonnet, Yvan Saeys, Dirk Stroobandt, Yves Van de Peer, Scalable hardware accelerator for comparing DNA and protein sequences., Infoscale 2006: 33
Philippe Grosse, Yves Durand, Paul Feautrier, Power Modeling of a NoC Based Design for High Speed Telecommunication Systems., PATMOS 2006: 157-168
Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini, SHAPES: : a tiled scalable software hardware architecture platform for embedded systems., CODES+ISSS 2006: 167-172
Pierre Amiranoff, Albert Cohen, Paul Feautrier, Beyond Iteration Vectors: Instancewise Relational Abstract Domains., SAS 2006: 161-180
Pierre Palatin, Yves Lhuillier, Olivier Temam, CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs., MICRO 2006: 247-258
Pieter Bellens, Josep M. Pérez, Rosa M. Badia, Jesús Labarta, Memory - CellSs: a programming model for the cell BE architecture., SC 2006: 86
Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii, Enabling fine-grain leakage management by voltage anchor insertion., DATE 2006: 868-873
Piotr Dziurzanski, W. Bielecki, Konrad Trifunovic, M. Kleszczonek, A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description., DDECS 2006: 153-154
Quan Shi, Ning Xi, Weihua Sheng, Yifan Chen, Development of Dynamic Inspection Methods for Dimensional Measurement of Automotive Body Parts., ICRA 2006: 315-320
Quan Shi, Ning Xi, Yifan Chen, Weihua Sheng, Registration of Point Clouds for 3D Shape Inspection., IROS 2006: 235-240
R. Castillo, Adrian Tineo, Francisco Corbera, Angeles G. Navarro, Rafael Asenjo, Emilio L. Zapata, Towards a Versatile Pointer Analysis Framework., Euro-Par 2006: 323-333
R. R. Osorio, J. D. Bruguera, High-Throughput Architecture for H.264/AVC CABAC Compression System, IEEE Trans. Circuits and Systems for Video Technology
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Improving the Flexibility of the Deficit Table Scheduler., HiPC 2006: 84-97
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Providing Quality of Service over Advanced Switching., ICPADS (1) 2006: 223-234
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Decoupling the Bandwidth and Latency Bounding for Table-based Schedulers., ICPP 2006: 155-163
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Studying Several Proposals for the Adaptation of the DTable Scheduler to Advanced Switching., ISPA 2006: 98-112
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Implementing the Advanced Switching Minimum Bandwidth Egress Link Scheduler., NCA 2006: 118-125
Raúl Sirvent, Josep M. Pérez, Rosa M. Badia, Jesús Labarta, Automatic Grid workflow based on imperative programming languages., Concurrency and Computation: Practice and Experience 18(10): 1169-1186 (2006)
Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser, Estimating Energy Consumption for an MPSoC Architectural Exploration., ARCS 2006: 298-310
Rachid Seghir, Vincent Loechner, Memory optimization by counting points in integer transformations of parametric polytopes., CASES 2006: 74-82
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida, Pre-synthesis optimization of multiplications to improve circuit performance., DATE 2006: 1306-1311
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, Applying the zeros switch-off technique to reduce static energy in data caches., SBAC-PAD 2006: 133-140
Rainer Buchty, Reconfigurable Architectures and Instruction Sets: Programmability Code Generation and Program Execution., Dynamically Reconfigurable Architectures 2006
Rainer Buchty, A Monitoring Infrastructure for the Digital on-demand Computing Organism (DodOrg)., IWSOS/EuroNGI 2006: 258
Rainer Buchty, Jie Tao, Wolfgang Karl, Automatic Data Locality Optimization Through Self-optimization., IWSOS/EuroNGI 2006: 187-201
Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, M. Pandey, A design flow for configurable embedded processors based on optimized instruction set extension synthesis., DATE 2006: 581-586
Ramon Nou, Ferran Julià, David Carrera, Kevin Hogan, Jordi Caubet, Jesús Labarta, Jordi Torres, Monitoring and analysing a Grid Middleware Node., GRID 2006: 309-310
Ramon Nou, Jordi Guitart, David Carrera, Jordi Torres, Experiences with Simulations - A Light and Fast Model for Secure Web Applications., ICPADS (1) 2006: 177-186
Raymond S. Wagner, Richard G. Baraniuk, Shu Du, David B. Johnson, Albert Cohen, An architecture for distributed wavelet analysis and processing in sensor networks., IPSN 2006: 243-250
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis, Improving SHA-2 Hardware Implementations., CHES 2006: 298-310
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis, Rescheduling for Optimized SHA-1 Calculation., SAMOS 2006: 425-434
Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, Leonel Sousa, Reconfigurable memory based AES co-processor., IPDPS 2006
Rickard Holsmark, Maurizio Palesi, Shashi Kumar, Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions., DSD 2006: 696-703
Robert G. Dimond, Oskar Mencer, Wayne Luk, Automating processor customisation: optimised memory access and resource sharing., DATE 2006: 206-211
Robert G. Dimond, Oskar Mencer, Wayne Luk, Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA., FCCM 2006: 175-184
Robert van Engelen, Madhusudhan Govindaraju, Nectarios Koziris, Kleanthis Psarris, Editorial message: special track on distributed systems and grid computing., SAC 2006: 739-740
Roberto Cordone, Fabrizio Ferrandi, Marco D. Santambrogio, Gianluca Palermo, Donatella Sciuto, Using speculative computation and parallelizing techniques to improve scheduling of control based designs., ASP-DAC 2006: 898-904
Roberto R. Osorio, Javier D. Bruguera, A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems, DSD '06: Proceedings of the 9th EUROMICRO Conference on Digital System Design, IEEE Computer Society, August 2006
Roberto R. Osorio, Javier D. Bruguera, High-Throughput Architecture for H.264/AVC CABAC Compression System, IEEE Trans. Circuits and Systems for Video Technology
Roberto R. Osorio, Javier D. Bruguera, A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems., DSD 2006: 269-274
Roberto R. Osorio, Javier D. Bruguera, High-Throughput Architecture for H.264/AVC CABAC Compression System., IEEE Trans. Circuits Syst. Video Techn. 16(11): 1376-1384 (2006)
Rodrigo Piedade, Leonel Sousa, Configurable Embedded Core for Controlling Electro-Mechanical Systems., ARC 2006: 18-23
Roland Ducournau, Etienne Gagnon, Chandra Krintz, Philippe Mulet, Jan Vitek, Olivier Zendra, Implementation Compilation Optimization of Object-Oriented Languages Programs and Systems., ECOOP Workshops 2006: 1-14
Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe, Statistical sampling of microarchitecture simulation., ACM Trans. Model. Comput. Simul. 16(3): 197-224 (2006)
Ron Gabor, Shlomo Weiss, Avi Mendelson, Fairness and Throughput in Switch on Event Multithreading., MICRO 2006: 149-160
Rosa Castillo, Adrian Tineo, Francisco Corbera, Angeles G. Navarro, Rafael Asenjo, Emilio L. Zapata, Towards a Versatile Pointer Analysis Framework., Euro-Par 2006: 323-333
Rosalia Christodoulopoulou, Kaloian Manassiev, Angelos Bilas, Cristiana Amza, Fast and transparent recovery for continuous availability of cluster-based servers., PPOPP 2006: 221-229
Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny, Fast Asynchronous Shift Register for Bit-Serial Communication., ASYNC 2006: 117-127
Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou, High Rate Data Synchronization in GALS SoCs., IEEE Trans. VLSI Syst. 14(10): 1063-1074 (2006)
Ruben Gran, Enric Morancho, Àngel Olivé, José María Llabería, An Enhancement for a Scheduling Logic Pipelined over two Cycles ., ICCD 2006
Rubing Duan, Radu Prodan, Thomas Fahringer, Run-time Optimisation of Grid Workflow Applications., GRID 2006: 33-40
Rubing Duan, Radu Prodan, Thomas Fahringer, Data Mining-based Fault Prediction and Detection on the Grid., HPDC 2006: 305-308
Rubino Geiß, Gernot Veit Batz, Daniel Grund, Sebastian Hack, Adam Szalkowski, GrGen: A Fast SPO-Based Graph Rewriting Tool., ICGT 2006: 383-397
Rudy Sicard, Thierry Artières, Eric Petit, Patch Learning for Incremental Classifier Design., ECAI 2006: 807-808
Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich, Higher-Dimensional Packing with Order Constraints., SIAM J. Discrete Math. 20(4): 1056-1078 (2006)
Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich, Minimizing Communication Cost for Reconfigurable Slot Modules., FPL 2006: 1-6
Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser, FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar., DSD 2006: 280-287
S. Bartolini, P. Foglia, C. A. Prete, Embedded processors and systems: Architectural issues and solutions for emerging applications, Journal of Embedded Computing , Volume 2 Issue 1, IOS Press, January 2006
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete, Memory performance: dealing with applications, systems and architecture, MEDEA '05: Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture, ACM, March 2006
S. Momcilovic, Tiago Dias, Nuno Roma, Leonel Sousa, Application Specific Instruction Set Processor for Adaptive Video Motion Estimation., DSD 2006: 160-167
Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Opens and Delay Faults in CMOS RAM Address Decoders., IEEE Trans. Computers 55(12): 1630-1639 (2006)
Salvador Petit, Julio Sahuquillo, Ana Pont, David R. Kaeli, Addressing a workload characterization study to the design of consistency protocols., The Journal of Supercomputing 38(1): 49-72 (2006)
Salvador Petit, Noel Tomás, Julio Sahuquillo, Ana Pont, An execution-driven simulation tool for teaching cache memories in introductory computer organization courses., WCAE 2006: 4
Sami Yehia, Jean-Francois Collard, Olivier Temam, Load squared: Adding logic close to memory to reduce the latency of indirect loads in embedded and general systems, Journal of Embedded Computing , Volume 2 Issue 1, IOS Press, January 2006
Sandrine Boumard, Matti Weissenfelt, Huageng Chi, Jari Nurmi, A Wireless MIMO STC OFDM System Implementation., PIMRC 2006: 1-5
Sandro Bartolini, Roberto Giorgi, Issues in Embedded Single-Chip Multicore Architectures, Journal of Embedded Computing , Volume 2 Issue 2, IOS Press, April 2006
Sarah Thompson, Alan Mycroft, Bit-level partial evaluation of synchronous circuits., PEPM 2006: 29-37
Sascha Uhrig, S. Maier, Georgi Kuzmanov, Theo Ungerer, Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling., IPDPS 2006
Sathish Chandra, Francesco Regazzoni, Marcello Lajolo, Hardware/software partitioning of operating systems: a behavioral synthesis approach., ACM Great Lakes Symposium on VLSI 2006: 324-329
Satish Narayanasamy, Gilles Pokam, Brad Calder, BugNet: Recording Application-Level Execution for Deterministic Replay Debugging., IEEE Micro 26(1): 100-109 (2006)
Scott Schneider, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Scalable locality-conscious multithreaded memory allocation., ISMM 2006: 84-94
Sebastian Hack, Daniel Grund, Gerhard Goos, Register Allocation for Programs in SSA-Form., CC 2006: 247-262
Seon Wook Kim, Chong-liang Ooi, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar, Exploiting reference idempotency to reduce speculative storage overflow., ACM Trans. Program. Lang. Syst. 28(5): 942-965 (2006)
Seongsoo Hong, Wayne Wolf, Krisztián Flautner, Taewhan Kim, Proceedings of the 2006 International Conference on Compilers Architecture and Synthesis for Embedded Systems CASES 2006 Seoul Korea October 22-25 2006, ACM 2006
Sergio Saponara, Pierangelo Terreni, Mixed-signal design of a digital input power amplifier for automotive audio applications., DATE Designers' Forum 2006: 212-216
Sherif Yusuf, Wayne Luk, M. K. N. Szeto, W. G. Osborne, UNITE: Uniform Hardware-Based Network Intrusion deTection Engine., ARC 2006: 389-400
Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Michael Kozuch, Todd C. Mowry, Radu Teodorescu, Anastassia Ailamaki, Limor Fix, Gregory R. Ganger, Bin Lin, Steven W. Schlosser, Log-based architectures for general-purpose monitoring of deployed code., ASID 2006: 63-65
Shinichi Yamagiwa, Leonel Sousa, Kevin Ferreira, Keiichi Aoki, Masaaki Ono, Koichi Wada, Maestro2: Experimental Evaluation of Communication Performance Improvement Techniques in the Link Layer., Journal of Interconnection Networks 7(2): 295-318 (2006)
Shiyong Lu, Feng Cao, Yi Lu, Pama: a Fast String Matching Algorithm., Int. J. Found. Comput. Sci. 17(2): 357-378 (2006)
Sid Ahmed Ali Touati, Denis Barthou, On the decidability of phase ordering problem in optimizing compilation., Conf. Computing Frontiers 2006: 147-156
Silvia Alayón, J. I. Estévez, Jose F. Sigut, José L. Sánchez, P. Toledo, An evolutionary Michigan recurrent fuzzy system for nuclei classification in cytological images using nuclear chromatin distribution., Journal of Biomedical Informatics: 573-588 (2006)
Simon Künzli, Francesco Poletti, Luca Benini, Lothar Thiele, Combining simulation and formal methods for system-level performance analysis., DATE 2006: 236-241
Simona Rossi, Daniele Masotti, Christine Nardini, Elena Bonora, Giovanni Romeo, Enrico Macii, Luca Benini, Stefano Volinia, TOM: a web-based integrated approach for identification of candidate disease genes., Nucleic Acids Research 34(Web-Server-Issue): 285-292 (2006)
Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo, Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA., ICSAMOS 2006: 107-114
Smaïl Niar, Nicolas Inglart, Rapid Performance and Power Consumption Estimation Methods for Embedded System Design., IEEE International Workshop on Rapid System Prototyping 2006: 47-53
Sonia González, Angeles G. Navarro, Juan López, Emilio L. Zapata, A Case Study of Load Sharing Based on Popularity in Distributed VoD Systems., IEEE Transactions on Multimedia 8(6): 1299-1304 (2006)
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk, Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs., ISQED 2006: 570-575
Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli, A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip., DAC 2006: 845-848
Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli, Mapping and configuration methods for multi-use-case networks on chips., ASP-DAC 2006: 146-151
Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli, A methodology for mapping multiple use-cases onto networks on chips., DATE 2006: 118-123
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo, Designing application-specific networks on chips with floorplan information., ICCAD 2006: 355-362
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo, Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips., VLSI-SoC 2006: 158-163
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz, PISC: Polymorphic Instruction Set Computers., ARC 2006: 274-286
Stamatis Vassiliadis, Ioannis Sourdis, FLUX Networks: Interconnects on Demand., ICSAMOS 2006: 160-167
Stamatis Vassiliadis, Stephan Wong, Timo Hämäläinen, Embedded Computer Systems: Architectures Modeling and Simulation 6th International Workshop SAMOS 2006 Samos Greece July 17-20 2006 Proceedings, Springer 2006
Stavros Papastavrou, George Samaras, Paraskevas Evripidou, Panos K. Chrysanthis, A decade of dynamic web content: A structured survey on past and present practices and future trends., IEEE Communications Surveys and Tutorials 8(1-4): 52-60 (2006)
Stavros Polyviou, George Samaras, Paraskevas Evripidou, Active Folders: A Metaphor for Developing and Interacting with Context-Aware Applications., MDM 2006: 146
Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner, Effective compiler generation by architecture description., LCTES 2006: 145-152
Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal, Profiling Driven Scenarion Detection and Prediction for Multimedia Applications., ICSAMOS 2006: 63-70
Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali, Supporting task migration in multi-processor systems-on-chip: a feasibility study., DATE 2006: 15-20
Stephane Piskorski, Lionel Lacassagne, Efficient 16-bit Floating-Point Interval Processor for Embedded Systems and Applications, SCAN '06: Proceedings of the 12th GAMM - IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN 2006) - Volume 00 , Volume 00, IEEE Computer Society, September 2006
Stephen Childs, Brian A. Coghlan, Jason McCandless, Dynamic Virtual Worker Nodes in a Production Grid., ISPA Workshops 2006: 417-426
Stephen Childs, Brian A. Coghlan, Jason McCandless, GridBuilder: A Tool for Creating Virtual Grid Testbeds., e-Science 2006: 77
Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos, Spatial Memory Streaming., ISCA 2006: 252-263
Steve Furber, Living with Failure: Lessons from Nature?, ETS '06: Proceedings of the Eleventh IEEE European Test Symposium (ETS'06) - Volume 00 , Volume 00, IEEE Computer Society, May 2006
Steve McKeever, Wayne Luk, Provably-correct hardware compilation tools based on pass separation techniques., Formal Asp. Comput. 18(2): 120-142 (2006)
Stijn Eyerman, James E. Smith, Lieven Eeckhout, Characterizing the branch misprediction penalty., ISPASS 2006: 48-58
Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere, Efficient design space exploration of high performance embedded out-of-order processors., DATE 2006: 351-356
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith, A performance counter architecture for computing accurate CPI components., ASPLOS 2006: 175-184
Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis, Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance., Computer Communications 29(13-14): 2612-2620 (2006)
Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Energy-efficient dynamic memory allocators at the middleware level of embedded systems., EMSOFT 2006: 215-222
Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems., DATE 2006: 874-875
Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk, A Flexible Multi-port Caching Scheme for Reconfigurable Platforms., ARC 2006: 205-216
Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk, Efficient Realtime FPGA Implementation of the Trace Transform., FPL 2006: 1-6
Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk, An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors., ISCIS 2006: 267-276
Sungroh Yoon, Luca Benini, Giovanni De Micheli, A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis., IEEE Trans. on CAD of Integrated Circuits and Systems 25(2): 358-377 (2006)
Sutjipto Arifin, Peter Y. K. Cheung, A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation., DATE Designers' Forum 2006: 227-232
Sutjipto Arifin, Peter Y. K. Cheung, Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System., FPL 2006: 1-4
Sutjipto Arifin, Peter Y. K. Cheung, User Attention Based Arousal Content Modeling., ICIP 2006: 433-436
Suzanne Rivoire, Rebecca Schultz, Tomofumi Okuda, Christos Kozyrakis, Vector Lane Threading., ICPP 2006: 55-64
Svetislav Momcilovic, Tiago Dias, Nuno Roma, Leonel Sousa, Application Specific Instruction Set Processor for Adaptive Video Motion Estimation., DSD 2006: 160-167
Sylvain Girbal, Nicolas Vasilache, Cédric Bastoul, Albert Cohen, David Parello, Marc Sigler, Olivier Temam, Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory Hierarchies., International Journal of Parallel Programming 34(3): 261-317 (2006)
T. Nachiondo, Jose Flich, José Duato, Destination-Based HoL Blocking Elimination., ICPADS (1) 2006: 213-222
T. Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé, Performance power efficiency and scalability of asymmetric cluster chip multiprocessors., Computer Architecture Letters 5(1): 14-17 (2006)
Taeho Kgil, Shaun D'Souza, Ali G. Saidi, Nathan L. Binkert, Ronald G. Dreslinski, Trevor N. Mudge, Steven K. Reinhardt, Krisztián Flautner, PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor., ASPLOS 2006: 117-128
Talal Bonny, Joerg Henkel, Using Lin-Kernighan algorithm for look-up table compression to improve code density, GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI, ACM, April 2006
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, A simple speculative load control mechanism for energy saving, MEDEA '06: Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, ACM, September 2006
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, Kilo-instruction processors runahead and prefetching., Conf. Computing Frontiers 2006: 269-278
Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala, Low-Power High-Performance TTA Processor for 1024-Point Fast Fourier Transform., SAMOS 2006: 227-236
Teresa Olivares, P. J. Tirado, Luis Orozco-Barbosa, Vicente López, P. Pedrón, Simulation of power-aware wireless sensor network architectures., PM2HW2N 2006: 32-39
Tero Arpinen, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications., DATE 2006: 1324-1329
Tero Kangas, Petri Kukkala, Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Jouni Riihimäki, Kimmo Kuusilinna, UML-based multiprocessor SoC design framework., ACM Trans. Embedded Comput. Syst. 5(2): 281-320 (2006)
Tero Kangas, Timo D. Hämäläinen, Kimmo Kuusilinna, Scalable Architecture for SoC Video Encoders., VLSI Signal Processing 44(1-2): 79-95 (2006)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, On-FPGA Communication Architectures and Design Factors., FPL 2006: 1-8
Tewolde Ghebregziabher, Jani Puttonen, Timo Hämäläinen, Ari Viinikainen, Security Analysis of Flow-based Fast Handover Method for Mobile IPv6 Networks., AINA (2) 2006: 849-853
Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, A Parallel Architecture for Hardware Face Detection., ISVLSI 2006: 452-453
Theocharis Theocharides / Vijay Narayanan, Embedded hardware face detection for digital surveillance systems, Embedded hardware face detection for digital surveillance systems, Pennsylvania State University, January 2006
Thierry Joffrain, Tze Meng Low, Enrique S. Quintana-Ortí, Robert A. van de Geijn, Field G. Van Zee, Accumulating Householder transformations revisited., ACM Trans. Math. Softw. 32(2): 169-179 (2006)
Thilo Streichert, Christian Haubelt, Jürgen Teich, Multi-Objective Topology Optimization for Networked Embedded Systems., ICSAMOS 2006: 93-98
Thilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich, Dynamic task binding for hardware/software reconfigurable networks., SBCCI 2006: 38-43
Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich, Modeling and design of fault-tolerant and self-adaptive reconfigurable networked embedded systems, EURASIP Journal on Embedded Systems , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe, Statistical sampling of microarchitecture simulation., IPDPS 2006
Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe, Simulation sampling with live-points., ISPASS 2006: 2-12
Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe, SimFlex: Statistical Sampling of Computer System Simulation., IEEE Micro 26(4): 18-31 (2006)
Thomas Fahringer, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks as part of the 24th IASTED International Multi-Conference on Applied Informatics February 14-16 2006 Innsbruck Austria, IASTED/ACTA Press 2006
Thomas Fahringer, Towards a sophisticated grid workflow development and computing environment., IPDPS 2006
Thomas J. Ashby, Anthony D. Kennedy, Stephen M. Watt, Coxeter Lattice Paths., Challenges in Symbolic Computation Software 2006
Thomas J. Ashby, Michael F. P. O'Boyle, Iterative Collective Loop Fusion., CC 2006: 202-216
Thomas Sødring, Raúl Martínez, Geir Horn, A Statistical Approach to Traffic Management in Source Routed Loss-Less Networks., HPCC 2006: 190-199
Thomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich, Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms., ISVLSI 2006: 309-316
Tiago Dias, Nuno Roma, Leonel Sousa, Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators., PATMOS 2006: 247-255
Tim Kogel, Rainer Leupers, Heinrich Meyr, Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms, Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms, Springer-Verlag New York, Inc., July 2006
Timo Vanhatupa, Marko Hännikäinen, Timo D. Hämäläinen, Evaluation of throughput estimation models and algorithms for WLAN frequency planning, QShine '06: Proceedings of the 3rd international conference on Quality of service in heterogeneous wired/wireless networks, ACM, August 2006
Timo Vogt, Christian Neeb, Norbert Wehn, A Reconfigurable Multi-Processor Platform for Convolutional and Turbo Decoding., ReCoSoC 2006: 16-23
Tiziana Gravagnoli, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, Automatic Test Pattern Generation with BOA., PPSN 2006: 423-432
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney, Aligning traces for performance evaluation., IPDPS 2006
Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng, Off-Line Testing of Delay Faults in NoC Interconnects., DSD 2006: 677-680
Tor Skeie, Svein Johannessen, Øyvind Holmeide, Timeliness of real-time IP communication in switched industrial Ethernet networks., IEEE Trans. Industrial Informatics 2(1): 25-39 (2006)
Torben Brack, Frank Kienle, Norbert Wehn, Disclosing the LDPC code decoder design space., DATE 2006: 200-205
Torben Brack, Matthias Alles, Frank Kienle, Norbert Wehn, A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding., PIMRC 2006: 1-5
Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, A SW performance estimation framework for early system-level-design using fine-grained instrumentation., DATE 2006: 468-473
Tudor Niculiu, Cristian Lupu, Sorin Cotofana, Consciousness for modeling intelligence - simulating the evolution by closure to the inverse., ICINCO-ICSO 2006: 187-190
Tuomas Järvinen, Perttu Salmela, Konsta Punkka, Jarmo Takala, Evaluation of stride permutation networks., ISCAS 2006
Uri Frank, Tsachy Kapschitz, Ran Ginosar, A predictive synchronizer for periodic clock domains., Formal Methods in System Design 28(2): 171-186 (2006)
Uwe Brinkschulte, Scalable Online Feasibility Tests for Admission Control in a Java Real-Time System., Real-Time Systems 32(3): 175-195 (2006)
Uwe Brinkschulte, Alexander von Renteln, Mathias Pacher, A Scheduling Strategy for a Real-Time Dependable Organic Middleware., SAMOS 2006: 339-348
Uwe Brinkschulte, Mathias Pacher, Florentin Picioroaga, Stefan Gaa, Evaluation of the Komodo Microcontroller and the OSA+ Middleware Using an Autonomous Guided Vehicle., ISORC 2006: 550-557
Víctor Reyes, Wido Kruijtzer, Tomás Bautista, Ghiath Alkadi, Antonio Núñez, A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study., DATE 2006: 474-479
Valentin Kravtsov, Thomas Niessen, Vlado Stankovski, Assaf Schuster, Service-based Resource Brokering for Grid-Based Data Mining., GCA 2006: 163-169
Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide, Cruz Izu, High-performance adaptive routing for networks with arbitrary topology., Journal of Systems Architecture 52(6): 345-358 (2006)
Valery Sklyarov, Iouliia Skliarova, E-learning Tools and Web-resources for Teaching Reconfigurable Systems., Education for the 21st Century 2006: 215-224
Valery Sklyarov, Iouliia Skliarova, Evolutionary Algorithm for State Encoding., IFIP AI 2006: 227-236
Valery Sklyarov, Iouliia Skliarova, Recursive and Iterative Algorithms for N-ary Search Problems., IFIP PPAI 2006: 81-90
Valery Sklyarov, Iouliia Skliarova, Multimedia Tools for Teaching Reconfigurable Systems., MoMM 2006: 211-220
Valery Sklyarov, Iouliia Skliarova, Reconfigurable Systems and their Influence on Mobile and Multimedia Applications., MoMM 2006: 7-8
Vanco B. Litovski, Miona Andrejevic, Mark Zwolinski, Analogue electronic circuit diagnosis based on ANNs., Microelectronics Reliability 46(8): 1382-1391 (2006)
Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson, Parallel depth first vs. work stealing schedulers on CMP architectures., SPAA 2006: 330
Vassos S. Soteriou / Li-Shiuan Peh, Run-time and design-time techniques towards power-efficient interconnection networks, Run-time and design-time techniques towards power-efficient interconnection networks, Princeton University, January 2006
Vassos Soteriou, Hangsheng Wang, Li-Shiuan Peh, A Statistical Traffic Model for On-Chip Interconnection Networks., MASCOTS 2006: 104-116
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh, Polaris: A System-Level Roadmap for On-Chip Interconnection Networks., ICCD 2006
Veerle Desmet, Lieven Eeckhout, Koen De Bosschere, Improved composite confidence mechanisms for a perceptron branch predictor., Journal of Systems Architecture 52(3): 143-151 (2006)
Veljko M. Milutinovic, Our Profession Needs a Reminder., IEEE Computer 39(5): 102-104 (2006)
Viay Holimath, Javier D. Bruguera, A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table., DSD 2006: 236-239
Vincent Nollet, Prabhat Avasare, Diederik Verkest, Henk Corporaal, Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment., ERSA 2006: 49-55
Weichao Wang, Bharat K. Bhargava, Yi Lu, Xiaoxin Wu, Defending against wormhole attacks in mobile ad hoc networks., Wireless Communications and Mobile Computing 6: 483-503 (2006)
Weihaw Chuang, Satish Narayanasamy, Ganesh Venkatesh, Jack Sampson, Michael Van Biesbrouck, Gilles Pokam, Brad Calder, Osvaldo Colavin, Unbounded page-based transactional memory., ASPLOS 2006: 347-358
Weihua Sheng, Girma S. Tewolde, Developing Active Sensor Networks with Micro Mobile Robots: Distributed Node Localization., FLAIRS Conference 2006: 478-483
Weihua Sheng, Girma S. Tewolde, Song Ci, Micro Mobile Robots in Active Sensor Networks: Closing the Loop., IROS 2006: 1440-1445
Weihua Sheng, Qingyan Yang, Jindong Tan, Ning Xi, Distributed multi-robot coordination in area exploration., Robotics and Autonomous Systems 54(12): 945-955 (2006)
Weihua Sheng, Qingyan Yang, Yi Guo, Cooperative Driving based on Inter-vehicle Communications: Experimental Platform and Algorithm., IROS 2006: 5073-5078
Weihua Sheng, Yantao Shen, Ning Xi, Mobile Sensor Navigation with Miniature Active Camera for Structure Inspection., IROS 2006: 1177-1182
Weizhe Zhang, Binxing Fang, Mingzeng Hu, Xinran Liu, Hongli Zhang, Lei Gao, Multisite co-allocation scheduling algorithms for parallel jobs in computing grid environments., Science in China Series F: Information Sciences 49(6): 906-926 (2006)
William Jalby, Christophe Lemuet, Sid Ahmed Ali Touati, An efficient memory operations optimization technique for vector loops on Itanium 2 processors., Concurrency and Computation: Practice and Experience 18(11): 1485-1508 (2006)
William Jalby, Oscar G. Plata, Barbara M. Chapman, Paul Kelly, Topic 4: Compilers for High Performance., Euro-Par 2006: 277
Wim Heirman, Joni Dambre, Jan M. Van Campenhout, Congestion modeling for reconfigurable inter-processor networks., SLIP 2006: 59-66
Wojciech Kabacinski, Marek Michalski, The Routing Algorithm and Wide-Sense Nonblocking Conditions for Multiplane Baseline Switching Networks., IEEE Journal on Selected Areas in Communications 24(S-12): 35-44 (2006)
Wolfgang Karl, Jürgen Becker, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle, ARCS 2006 - 19th International Conference on Architecture of Computing Systems Workshops Proceedings March 16 2006 Frankfurt am Main Germany, GI 2006
Wolfgang Trumler, Jan Petzold, Faruk Bagci, Theo Ungerer, AMUN: an autonomic middleware for the Smart Doorplate Project., Personal and Ubiquitous Computing 10(1): 7-11 (2006)
Wolfgang Trumler, Robert Klaus, Theo Ungerer, Self-configuration Via Cooperative Social Behavior., ATC 2006: 90-99
Wolfgang Trumler, Tobias Thiemann, Theo Ungerer, An Artificial Hormone System for Self-organization of Networked Nodes., BICC 2006: 85-94
Wouter Caarls, Pieter P. Jonker, Henk Corporaal, Algorithmic skeletons for stream programming in embedded heterogeneous parallel image processing applications., IPDPS 2006
Wouter Caarls, Pieter P. Jonker, Henk Corporaal, Skeletons and Asynchronous RPC for Embedded Data and Task Parallel Image Processing., IEICE Transactions 89-D(7): 2036-2043 (2006)
Xavier Martorell, Marc González, Alejandro Duran, Jairo Balart, Roger Ferrer, Eduard Ayguadé, Jesús Labarta, Techniques supporting threadprivate in OpenMP., IPDPS 2006
Xiaoning Ding, Dimitrios S. Nikolopoulos, Song Jiang, Xiaodong Zhang, MESA: reducing cache conflicts by integrating static and run-time methods., ISPASS 2006: 189-198
Xiaoyuan Yang, Porfidio Hernández, Fernando Cores, Ana Ripoll, Remo Suppi, Emilio Luque, Providing VCR in a Distributed Client Collaborative Multicast Video Delivery Scheme., Euro-Par 2006: 777-787
Xiaoyuan Yang, Porfidio Hernández, Fernando Cores, Leandro Souza, Ana Ripoll, Remo Suppi, Emilio Luque, DVoDP/sup 2/P: distributed P2P assisted multicast VoD architecture., IPDPS 2006
Xin Wang, Tapani Ahonen, Jari Nurmi, Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools., FPL 2006: 1-6
Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, A Spatiotemporal Saliency Framework., ICIP 2006: 437-440
Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley, Hardware efficient architectures for Eigenvalue computation., DATE 2006: 953-958
Yang Qu, Juha-Pekka Soininen, Jari Nurmi, A parallel configuration model for reducing the run-time reconfiguration overhead., DATE 2006: 965-969
Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz, Michael Vinov, Eitan Marcus, Gil Shurek, Constraint-Based Random Stimuli Generation for Hardware Verification., AAAI 2006
Yehuda Sadeh Weinraub, Shlomo Weiss, Power-aware out-of-order issue logic in high-performance microprocessors., Microprocessors and Microsystems 30(7): 457-467 (2006)
Yi Lu / Shiyong Lu, Advanced data mining techniques for identifying correlation between gene expression and promoters, Advanced data mining techniques for identifying correlation between gene expression and promoters, Wayne State University, January 2006
Yi Lu, Adrian E. Platts, G. Charles Ostermeier, Stephen A. Krawetz, K-SPMM: a database of murine spermatogenic promoters modules & motifs., BMC Bioinformatics 7: 238 (2006)
Yi Lu, Shiyong Lu, Adrian E. Platts, Stephen A. Krawetz, Mining Correlation between Motifs and Gene Expression., ICDM 2006: 986-990
Yi Lu, Shiyong Lu, Farshad Fotouhi, Yan Sun, Zijiang Yang, Lily R. Liang, PDC: Pattern discovery with confidence in DNA sequences., ACST 2006: 345-350
Yi Lu, Shiyong Lu, Jeffrey L. Ram, Fast search in DNA sequence databases using punctuation and indexing., ACST 2006: 351-356
Yi Lu, Shiyong Lu, Lily R. Liang, Deepak Kumar, FM-test: A Fuzzy Set Theory Based Approach for Discovering Diabetes Genes., IMSCCS (1) 2006: 48-55
Yi Lu, Weichao Wang, Bharat K. Bhargava, Dongyan Xu, Trust-based privacy preservation for peer-to-peer data sharing., IEEE Transactions on Systems Man and Cybernetics Part A 36(3): 498-502 (2006)
Yitzhak Birk, Idit Keidar, Liran Liss, Assaf Schuster, Efficient Dynamic Aggregation., DISC 2006: 90-104
Yitzhak Birk, Idit Keidar, Liran Liss, Assaf Schuster, Ran Wolff, Veracity radius: capturing the locality of distributed computations., PODC 2006: 102-111
Yoav Etsion, Dan Tsafrir, Dror G. Feitelson, Process prioritization using output production: Scheduling for multimedia., TOMCCAP 2(4): 318-342 (2006)
Yolanda Becerra, Jordi Garcia, Toni Cortes, Nacho Navarro, Java Virtual Machine: the key for accurated memory prefetching., Software Engineering Research and Practice 2006: 933-939
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner, SODA: A Low-power Architecture For Software Radio., ISCA 2006: 89-101
Yunhe Shi, Emre Özer, David Gregg, Low-Cost Microarchitectural Techniques for Enhancing the Prediction of Return Addresses on High-Performance Trace Cache Processors., ISCIS 2006: 248-257
Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Space of DRAM fault models and corresponding testing., DATE 2006: 1252-1257
Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi, Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs., IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2989-2996 (2006)
Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari, HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems., Microprocessors and Microsystems 30(2): 72-85 (2006)
Zsolt Németh, Michail Flouris, Renaud Lachaize, Angelos Bilas, Support for Automatic Diagnosis and Dynamic Configuration of Scalable Storage Systems., Euro-Par Workshops 2006: 15-21
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny, Efficient link capacity and QoS design for network-on-chip., DATE 2006: 9-14

2007

Ahmed Abdel-Hafez, Ali Miri, Luis Orozco-Barbosa, Authenticated Group Key Agreement Protocols for Ad hoc Wireless Networks., I. J. Network Security 4(1): 90-98 (2007)
Alessio Bechini, Andrea Tomasi, Jacopo Viotto, Document Management for Collaborative e-Business: Integrating EBXML Environment and Legacy DMS., ICE-B 2007: 78-83
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere, Classifying interprocess communication in process network representation of nested-loop programs., ACM Trans. Embedded Comput. Syst. 6(2): (2007)
Christoph W. Kessler, Andrzej Bednarski, Mattias V. Eriksson, Classification and generation of schedules for VLIW processors., Concurrency and Computation: Practice and Experience 19(18): 2369-2389 (2007)
Christoph W. Kessler, Welf Löwe, A Framework for Performance-Aware Composition of Explicitly Parallel Components., PARCO 2007: 227-234
Giovanni Agosta, Gerardo Pelosi, A Domain Specific Language for Cryptography., FDL 2007: 159-164
Giovanni Agosta, Luca Breveglieri, Gerardo Pelosi, Israel Koren, Countermeasures against Branch Target Buffer Attacks., FDTC 2007: 75-79
Giovanni Agosta, Luca Breveglieri, Gerardo Pelosi, Martino Sykora, Programming Highly Parallel Reconfigurable Architectures for Public-Key Cryptographic Applications., ITNG 2007: 3-10
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere, Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips., FPL 2007: 580-584
José M. Badía, Peter Benner, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Alfredo Remón, Parallel Implementation of LQG Balanced Truncation for Large-Scale Systems., LSSC 2007: 227-234
Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran, , RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks., DAC 2007: 489-492
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano, , A data protection unit for NoC-based architectures., CODES+ISSS 2007: 167-172
M. Danish, Arees Qamareen, Shashi Kumar, Surendra Kumar, Letter to the Editor., Computers & Chemical Engineering 31(10): 1364-1365 (2007)
Mikel Luján, Phyllis Gustafson, Michael Paleczny, Christopher A. Vick, Speculative Parallelization - Eliminating the Overhead of Failure., HPCC 2007: 460-471
Mikhail Chalabine, Christoph W. Keßler, A Survey of Reasoning in Parallelization., SNPD (3) 2007: 629-634
Mikhail Chalabine, Christoph W. Kessler, A Formal Framework for Automated Round-Trip Software Engineering in Static Aspect Weaving and Transformations., ICSE 2007: 137-146
Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere, Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation., IEEE Transactions on Signal Processing 55(6-2): 3126-3138 (2007)
Mohamed Hussein, Kenneth R. Mayes, Mikel Luján, John R. Gurd, Adaptive performance control for distributed scientific coupled models., ICS 2007: 274-283
N. Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krish, Future generation supercomputers II: a paradigm for cluster architecture., SIGARCH Computer Architecture News 35(5): 61-70 (2007)
Pablo Ituero, José L. Ayala, Marisa López-Vallejo, Leakage-based On-Chip Thermal Sensor for CMOS Technology., ISCAS 2007: 3327-3330
Perttu Salmela, Chung-Ching Shen, Shuvra S. Bhattacharyya, Jarmo Takala, Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations., SiPS 2007: 475-480
Perttu Salmela, Juho Antikainen, Olli Silvén, Jarmo Takala, Memory-Based List Updating for List Sphere Decoders., SiPS 2007: 633-638
Reiner Hartenstein, , The Neumann Syndrome calls for a revolution., HPRCTA 2007
Saeed Samet, Ali Miri, Luis Orozco-Barbosa, Privacy Preserving k-Means Clustering in Multi-Party Environment., SECRYPT 2007: 381-385
Stéphanie Lanche, Tron A. Darvann, Hildur Ólafsdóttir, Nuno V. Hermann, Andrea E. Van Pelt, Daniel Govier, Marissa J. Tenenbaum, Sybill Naidoo, Per Larsen, Sven Kreiborg, Rasmus , A Statistical Model of Head Asymmetry in Infants with Deformational Plagiocephaly., SCIA 2007: 898-907
Vanderlei Bonato, Eduardo Marques, George A. Constantinides, A floating-point Extended Kalman Filter implementation for autonomous mobile robots., FPL 2007: 576-579
Zoran Babovic, Darko Jovic, Veljko M. Milutinovic, Survey of eGovernment Services in Serbia., Informatica (Slovenia) 31(4): 379-396 (2007)
Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi, A radix-10 SRT divider based on alternative BCD codings., ICCD 2007: 280-287
Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi, A New Family of High.Performance Parallel Decimal Multipliers., IEEE Symposium on Computer Arithmetic 2007: 195-204
Åshild Grønstad Solheim, Olav Lysne, Thomas Sødring, Tor Skeie, Jakob Aleksander Libak, Routing-Contained Virtualization Based on Up*/Down* Forwarding., HiPC 2007: 500-513
Éric Piel, Philippe Marquet, Jean-Luc Dekeyser, Model Transformations for the Compilation of Multi-processor Systems-on-Chip., GTTSE 2007: 459-473
A. Bai, Tor Skeie, Paal E. Engelstad, A Model-Based Admission Control for 802.11e EDCA using Delay Predictions., IPCCC 2007: 226-235
A. Bardine, P. Foglia, G. Gabrielli, C. A. Prete, P. Stenström, Improving power efficiency of D-NUCA caches, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
A. Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie, Boosting Ethernet Performance by Segment-Based Routing., PDP 2007: 55-62
Abbas Bigdeli, Colin Sim, Morteza Biglari-Abhari, Brian C. Lovell, Face Detection on Embedded Systems., ICESS 2007: 295-308
Afrin Naz, Krishna M. Kavi, Jung-Hwan Oh, Pierfrancesco Foglia, Reconfigurable split data caches: a novel scheme for embedded systems., SAC 2007: 707-712
Aggelos Ioannou, Manolis Katevenis, Pipelined heap (priority queue) management for advanced scheduling in high-speed networks., IEEE/ACM Trans. Netw. 15(2): 450-461 (2007)
Ahmad Zmily, Christos Kozyrakis, A low power front-end for embedded processors using a block-aware instruction set., CASES 2007: 267-276
Ajay K. Verma, Paolo Ienne, Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands., ASP-DAC 2007: 601-608
Ajay K. Verma, Paolo Ienne, Automatic synthesis of compressor trees: reevaluating large counters., DATE 2007: 443-448
Ajay K. Verma, Philip Brisk, Paolo Ienne, Rethinking custom ISE identification: a new processor-agnostic method., CASES 2007: 125-134
Ajay K. Verma, Philip Brisk, Paolo Ienne, Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits., DAC 2007: 404-409
Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, Exploring the Application Behavior Space Using Parameterized Synthetic Benchmarks., PACT 2007: 412
Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal, Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip., DATE 2007: 117-122
Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha, A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices., DAC 2007: 726-731
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal, Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA., FPL 2007: 92-97
Alain Darte, C. Quinson, Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis., ASAP 2007: 140-147
Alan Mycroft, Programming Language Design and Analysis Motivated by Hardware Evolution., SAS 2007: 18-33
Alastair F. Donaldson, Colin Riley, Anton Lokhmotov, Andrew Cook, Auto-parallelisation of Sieve C++ Programs., Euro-Par Workshops 2007: 18-27
Alberto Ros, Manuel E. Acacio, José M. García, Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors., HiPC 2007: 147-160
Alejandro Calderón, Félix García Carballeira, Florin Isaila, Rainer Keller, Alexander Schulz, Fault Tolerant File Models for MPI-IO Parallel File Systems., PVM/MPI 2007: 153-160
Alejandro Calderón, Félix García Carballeira, Luis Miguel Sánchez, José Daniel García, Javier Fernández, Fault tolerant file models for parallel file systems: distribution pattern flexibility and its reliability., PDPTA 2007: 676-682
Alejandro Duran, Roger Ferrer, Juan José Costa, Marc González, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, A Proposal for Error Handling in OpenMP., International Journal of Parallel Programming 35(4): 393-416 (2007)
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, Francisco J. Quiles, José Duato, A New Cost-Effective Technique for QoS Support in Clusters., IEEE Trans. Parallel Distrib. Syst. 18(12): 1714-1726 (2007)
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Providing Full QoS with 2 VCs in High-Speed Switches., ICOIN 2007: 345-354
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Efficient Switches with QoS Support for Clusters., IPDPS 2007: 1-6
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Deadline-based QoS Algorithms for High-performance Networks., IPDPS 2007: 1-9
Alejandro Martínez, Raúl Martínez, Francisco José Alfaro, José L. Sánchez, A low-cost strategy to provide full QoS support in Advanced Switching networks., Journal of Systems Architecture 53(7): 355-368 (2007)
Alejandro Martínez-Vicente, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, Jose Flich, Francisco J. Quiles, José Duato, Integrated QoS Provision and Congestion Management for Interconnection Networks., Euro-Par 2007: 837-847
Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Analysis of static and dynamic energy consumption in NUCA caches: initial results, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Alessandro Dalla Torre, Martino Ruggiero, Luca Benini, MP-Queue: an Efficient Communication Library for Embedded Streaming Multimedia Platforms., ESTImedia 2007: 105-110
Alessandro G. Di Nuovo, Maurizio Palesi, Vincenzo Catania, Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems., FUZZ-IEEE 2007: 1-6
Alessandro G. Di Nuovo, Vincenzo Catania, On External Measures for Validation of Fuzzy Partitions., IFSA (1) 2007: 491-501
Alex E. Susu, Michele Magno, Andrea Acquaviva, David Atienza, Giovanni De Micheli, Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation., T. HiPEAC 1: 341-360 (2007)
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Using fine grain multithreading for energy efficient computing., PPOPP 2007: 259-269
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gregory Shklover, Code Compilation for an Explicitly Parallel Register-Sharing Architecture., ICPP 2007: 58
Alex Villazón, Malik Junaid, Mumtaz Siddiqui, Thomas Fahringer, Applying patterns for porting complex workflows onto the Grid., CoreGRID 2007: 265-275
Alexander Sayenko, Olli Alanen, Timo Hämäläinen, On Contention Resolution Parameters for the IEEE 802.16 Base Station., GLOBECOM 2007: 4957-4962
Alexander Sayenko, Olli Alanen, Timo Hämäläinen, Adaptive Contention Resolution for VoIP Services in the IEEE 802.16 Networks., WOWMOM 2007: 1-7
Alexandros Stamatakis, Filip Blagojevic, Dimitrios S. Nikolopoulos, Christos D. Antonopoulos, Exploring New Search Algorithms and Hardware for Phylogenetics: RAxML Meets the IBM Cell., VLSI Signal Processing 48(3): 271-286 (2007)
Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich, Efficient event-driven simulation of parallel processor architectures., SCOPES 2007: 71-80
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement, Modeling of Interconnection Networks in Massively Parallel Processor Architectures., ARCS 2007: 268-282
Alfredo Remón, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, The Implementation of BLAS for Band Matrices., PPAM 2007: 668-677
Alfredo Remón, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Parallel Solution of Band Linear Systems in Model Reduction., PPAM 2007: 678-687
Ali Ahmadinia, Christophe Bobda, Sandor P. Fekete, Jurgen Teich, Jan C. van der Veen, Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices, IEEE Transactions on Computers , Volume 56 Issue 5, IEEE Computer Society, May 2007
Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha, Transactional programming in a multi-core environment., PPOPP 2007: 272
Ali-Reza Adl-Tabatabai, David Dice, Maurice Herlihy, Nir Shavit, Christos Kozyrakis, Christoph von Praun, Michael Scott, Potential show-stoppers for transactional synchronization., PPOPP 2007: 55
Aliaksei Kerhet, Francesco Leonardi, Andrea Boni, Paolo Lombardo, Michele Magno, Luca Benini, Distributed video surveillance using hardware-friendly sparse large margin classifiers., AVSS 2007: 87-92
Aliaksei Kerhet, Michele Magno, Francesco Leonardi, Andrea Boni, Luca Benini, A low-power wireless video sensor node for distributed object detection., J. Real-Time Image Processing 2(4): 331-342 (2007)
Alicia Asín Pérez, Darío Suárez Gracia, Victor Viñals Yúfera, A proposal to introduce power and energy notions in computer architecture laboratories, WCAE '07: Proceedings of the 2007 workshop on Computer architecture education, ACM, June 2007
Amedeo Cesta, Gabriella Cortellessa, Michel Denis, Alessandro Donati, Simone Fratini, Angelo Oddi, Nicola Policella, Erhard Rabenau, Jonathan Schulster, Mexar2: AI Solves Mission Planner Problems., IEEE Intelligent Systems 22(4): 12-19 (2007)
Amit D. Lakhani, Erica Y. Yang, Brian Matthews, Ian Johnson, Syed Naqvi, Gheorghe Cosmin Silaghi, Threat Analysis and Attacks on XtreemOS: a Grid-enabled Operating System., CoreGRID 2007: 53-62
Amund Kvalbein, Olav Lysne, How can multi-topology routing be used for intradomain traffic engineering?, INM '07: Proceedings of the 2007 SIGCOMM workshop on Internet network management, ACM, August 2007
Ana Bosque, Pablo Ibañez, Víctor Viñals, Per Stenström, Jose M. Llabería, Characterization of Apache web server with Specweb2005, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Ana Lucia Varbanescu, Henk J. Sips, Kenneth A. Ross, Qiang Liu, Lurng-Kuo Liu, Apostol Natsev, John R. Smith, An Effective Strategy for Porting C++ Applications on Cell., ICPP 2007: 59
Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven, Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors., T. HiPEAC 1: 279-297 (2007)
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg Henkel, Instruction trace compression for rapid instruction cache simulation, DATE '07: Proceedings of the conference on Design, automation and test in Europe, EDA Consortium, April 2007
Andrés Marín López, Daniel Díaz Sánchez, Florina Almenárez, Carlos García Rubio, Celeste Campo, Smart card-based agents for fair non-repudiation, Computer Networks: The International Journal of Computer and Telecommunications Networking , Volume 51 Issue 9, Elsevier North-Holland, Inc., June 2007
André C. Nácul, Francesco Regazzoni, Marcello Lajolo, Hardware scheduling support in SMP architectures., DATE 2007: 642-647
Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology., ACM Great Lakes Symposium on VLSI 2007: 501-504
Andrea Marongiu, Luca Benini, Mahmut T. Kandemir, Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms., CASES 2007: 145-149
Andreas Hansson, Kees Goossens, Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases., NOCS 2007: 233-242
Andreas Hansson, Martijn Coenen, Kees Goossens, Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip., CODES+ISSS 2007: 149-154
Andreas Hansson, Martijn Coenen, Kees Goossens, Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip., DATE 2007: 954-959
Andrei Terechko, Henk Corporaal, Inter-cluster communication in VLIW architectures., TACO 4(2): (2007)
Andres Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie, Boosting Ethernet Performance by Segment-Based Routing., PDP 2007: 55-62
Andy Georges, Dries Buytaert, Lieven Eeckhout, Statistically rigorous java performance evaluation., OOPSLA 2007: 57-76
Andy Georges, Dries Buytaert, Lieven Eeckhout, Adding rigorous statistics to the Java benchmarker's toolbox., OOPSLA Companion 2007: 793-794
Angeles G. Navarro, Francisco Corbera, Adrian Tineo, Rafael Asenjo, Emilio L. Zapata, Detecting loop-carried dependences in programs with dynamic data structures., J. Parallel Distrib. Comput. 67(1): 47-62 (2007)
Angelo Duarte, Dolores Rexachs, Emilio Luque, Functional Tests of the RADIC Fault Tolerance Architecture., PDP 2007: 278-287
Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto, A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis., ISVLSI 2007: 92-97
Ani Nahapetian, Paolo Lombardo, Andrea Acquaviva, Luca Benini, Majid Sarrafzadeh, Dynamic reconfiguration in sensor networks with regenerative energy sources., DATE 2007: 1054-1059
Anna Antola, Marco Castagna, Pamela Gotti, Marco D. Santambrogio, Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseC., ERSA 2007: 216-219
Anna Morajko, Paola Caymes-Scutari, Tomàs Margalef, Emilio Luque, MATE: Monitoring Analysis and Tuning Environment for parallel/distributed applications., Concurrency and Computation: Practice and Experience 19(11): 1517-1531 (2007)
Anna Morajko, Tomàs Margalef, Emilio Luque, Design and implementation of a dynamic tuning environment., J. Parallel Distrib. Comput. 67(4): 474-490 (2007)
Antoine Fraboulet, Guillaume Chelius, Eric Fleury, Worldsens: development and prototyping tools for application specific wireless sensors networks., IPSN 2007: 176-185
Antoine Fraboulet, Tanguy Risset, Master Interface for On-chip Hardware Accelerator Burst Communications., VLSI Signal Processing 49(1): 73-85 (2007)
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset, Long-Range Dependence and On-chip Processor Traffic., ReCoSoC 2007: 111-120
Anton Lokhmotov, Alan Mycroft, Optimal bit-reversal using vector permutations., SPAA 2007: 198-199
Anton Lokhmotov, Alan Mycroft, Andrew Richards, Delayed Side-Effects Ease Multi-core Programming., Euro-Par 2007: 641-650
Anton Lokhmotov, Benedict R. Gaster, Alan Mycroft, Neil Hickey, David Stuttard, Revisiting SIMD Programming., LCPC 2007: 32-46
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, An Interrupt Controller for FPGA-based Multiprocessors., ICSAMOS 2007: 82-87
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, A design kit for a fully working shared memory multiprocessor on FPGA., ACM Great Lakes Symposium on VLSI 2007: 219-222
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, A Self-Reconfigurable Implementation of the JPEG Encoder., ASAP 2007: 24-29
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs., ISVLSI 2007: 331-336
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb., ISVLSI 2007: 449-450
Antonio Flores, Juan L. Aragón, Manuel E. Acacio, Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures., AINA Workshops (1) 2007: 752-757
Antonio Flores, Juan L. Aragón, Manuel E. Acacio, Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network., HiPC 2007: 133-146
Antonio J. Dorta, José M. Badía, Enrique S. Quintana-Ortí, Francisco de Sande, Parallelizing Dense Linear Algebra Operations with Task Queues in., PVM/MPI 2007: 89-96
Antonio Ortiz, Teresa Olivares, Luis Orozco-Barbosa, A heterogeneous role-based sensor network., PM2HW2N 2007: 61-67
Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini, NoC Design and Implementation in 65nm Technology., NOCS 2007: 273-282
Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini, Bringing NoCs to 65 nm., IEEE Micro 27(5): 75-85 (2007)
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, Implementing the Advanced Switching Fabric Discovery Process., IPDPS 2007: 1-8
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, A Complete Topology Management Mechanism for the Advanced Switching Interconnect Technology., ISCC 2007: 893-899
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, Tor Skeie, A distributed approach to handle topological changes in advanced switching., PM2HW2N 2007: 37-44
Antonis Papadogiannakis, Demetres Antoniades, Michalis Polychronakis, Evangelos P. Markatos, Improving the Performance of Passive Network Monitoring Applications using Locality Buffering., MASCOTS 2007: 151-157
Antony Chazapis, Georgios Tsoukalas, Georgios Verigakis, Kornilios Kourtis, Aristidis Sotiropoulos, Nectarios Koziris, Global-scale peer-to-peer file services with DFS., GRID 2007: 251-258
Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen, IP Integration Overhead Analysis in System-on-Chip Video Encoder., DDECS 2007: 333-336
Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Design space exploration of partially re-configurable embedded processors., DATE 2007: 319-324
Anupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors., IEEE International Workshop on Rapid System Prototyping 2007: 189-194
Arash Ahmadi, Mark Zwolinski, Multiple-Width Bus Partitioning Approach to Datapath Synthesis., ISCAS 2007: 2994-2997
Ari Kulmala, Erno Salminen, Timo D. Hämäläinen, Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder., DDECS 2007: 105-110
Ari Kulmala, Erno Salminen, Timo D. Hämäläinen, Evaluating Large System-on-Chip on Multi-FPGA Platform., SAMOS 2007: 179-189
Arnaud Verdant, Antoine Dupret, Hervé Mathias, Patrick Villard, Lionel Lacassagne, Adaptive Multiresolution for Low Power CMOS Image Sensor., ICIP (5) 2007: 185-188
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, SIMD Vectorization of Histogram Functions., ASAP 2007: 174-179
Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing., DATE 2007: 1544-1549
Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Timing-driven row-based power gating., ISLPED 2007: 104-109
Audun Fosselie Hansen, Olav Lysne, Tarik Cicic, Stein Gjessing, Fast Proactive Recovery from Concurrent Failures., ICC 2007: 115-122
Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, José Duato, Handling Topology Changes in InfiniBand., IEEE Trans. Parallel Distrib. Syst. 18(2): 172-185 (2007)
Austen McDonald, Brian D. Carlstrom, JaeWoong Chung, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun, Transactional Memory: The Hardware-Software Interface., IEEE Micro 27(1): 67-76 (2007)
Avi Mendelson, Current trends in computer architectures: multi-cores many-cores and special-cores., ICS 2007: 1
Avi Nissimov, Dror G. Feitelson, Probabilistic Backfilling., JSSPP 2007: 102-115
Avraam N. Chimaris, George A. Papadopoulos, Implementing a generic component-based framework for telecontrol applications, Software—Practice & Experience , Volume 37 Issue 10, John Wiley & Sons, Inc., August 2007
Ayelet Israeli, Dror G. Feitelson, Success of Open Source Projects: Patterns of Downloads and Releases with Time., SwSTE 2007: 87-94
Ayose Falcón, Paolo Faraboschi, Daniel Ortega, Combining Simulation and Virtualization through Dynamic Sampling., ISPASS 2007: 72-83
B. de la Ossa, J. A. Gil, J. Sahuquillo, A. Pont, Web prefetch performance evaluation in a real environment, LANC '07: Proceedings of the 4th international IFIP/ACM Latin American conference on Networking, ACM, October 2007
B. de la Ossa, José A. Gil, Julio Sahuquillo, Ana Pont, Delfos: the Oracle to Predict NextWeb User's Accesses., AINA 2007: 679-686
B. Prados-Suárez, J. Chamorro-Martínez, D. Sánchez, J. Abad, Region-based fit of color homogeneity measures for fuzzy image segmentation, Fuzzy Sets and Systems , Volume 158 Issue 3, Elsevier North-Holland, Inc., February 2007
Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek, Communication-Centric SoC Debug Using Transactions., European Test Symposium 2007: 69-76
Bas Breijer, Filipa Duarte, Stephan Wong, An OCM based shared Memory controller for Virtex 4., FPL 2007: 692-696
Beatriz Otero, José M. Cela, A Workload Distribution Pattern for Grid Environments., GCA 2007: 56-62
Behnaz Pourebrahimi, Koen Bertels, Fair access to scarce resources in ad-hoc grids using an economic-based approach., MGC 2007: 8
Behnaz Pourebrahimi, S. Arash Ostadzadeh, Koen Bertels, Resource Allocation in Market-based Grids Using a History-based Pricing Mechanism., SCSS (1) 2007: 97-100
Ben Cope, Peter Y. K. Cheung, Wayne Luk, Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective., ASAP 2007: 308-313
Benjamin Satzger, Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, Variations and Evaluations of an Adaptive Accrual Failure Detector to Enable Self-healing Properties in Distributed Systems., ARCS 2007: 171-184
Benjamin Satzger, Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, A new adaptive accrual failure detector for dependable distributed systems., SAC 2007: 551-555
Benjamin Satzger, Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, A new adaptive accrual failure detector for dependable distributed systems, SAC '07: Proceedings of the 2007 ACM symposium on Applied computing, ACM, March 2007
Benny Akesson, Kees Goossens, Markus Ringhofer, Predator: a predictable SDRAM memory controller., CODES+ISSS 2007: 251-256
Bertrand Anckaert, Mariusz H. Jakubowski, Ramarathnam Venkatesan, Koen De Bosschere, Run-Time Randomization to Mitigate Tampering., IWSEC 2007: 153-168
Bertrand Anckaert, Matias Madou, Bjorn De Sutter, Bruno De Bus, Koen De Bosschere, Bart Preneel, Program obfuscation: a quantitative approach., QoP 2007: 15-20
Bhuvaneswari Arunachalan, Janet Light, Ian Watson, Mobile Agent Based Messaging Mechanism for Emergency Medical Data Transmission Over Cellular Networks., COMSWARE 2007
Bill Lin, Isaac Keslassy, Frame-aggregated concurrent matching switch., ANCS 2007: 107-116
Biplav Srivastava, Tuan A. Nguyen, Alfonso Gerevini, Subbarao Kambhampati, Minh Binh Do, Ivan Serina, Domain independent approaches for finding diverse plans, IJCAI'07: Proceedings of the 20th international joint conference on Artifical intelligence, Morgan Kaufmann Publishers Inc., January 2007
Björn Nilsson, Lars Bengtsson, Per-Arne Wiberg, Bertil Svensson, Protocols for Active RFID - The Energy Consumption Aspect., SIES 2007: 41-48
Bjorn De Sutter, Ludo Van Put, Dominique Chanet, Bruno De Bus, Koen De Bosschere, Link-time compaction and optimization of ARM executables., ACM Trans. Embedded Comput. Syst. 6(1): (2007)
Bjorn De Sutter, Ludo Van Put, Koen De Bosschere, A practical interprocedural dominance algorithm., ACM Trans. Program. Lang. Syst. 29(4): (2007)
Blas Cuesta, Antonio Robles, José Duato, An Effective Starvation Avoidance Mechanism to Enhance the Token Coherence Protocol., PDP 2007: 47-54
Bratislav Predic, Dejan Rančic, Dragan Stojanovic, Aleksandar Milosavljevic, Automatic vehicle location in public bus transportation system, ICCOMP'07: Proceedings of the 11th WSEAS International Conference on Computers, World Scientific and Engineering Academy and Society (WSEAS), July 2007
Brian D. Carlstrom, Austen McDonald, Michael Carbin, Christos Kozyrakis, Kunle Olukotun, Transactional collection classes., PPOPP 2007: 56-67
C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet, Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter., DATE 2007: 177-182
C. P. Ravikumar, Jari Nurmi, Conference Reports., IEEE Design & Test of Computers 24(2): 202-203 (2007)
Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy, Synthesis of Multimode digital signal processing systems., AHS 2007: 318-325
Cagkan Erbas, Andy D. Pimentel, Mark Thompson, Simon Polstra, A framework for system-level modeling and simulation of embedded systems architectures, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Cagkan Erbas, Andy D. Pimentel, Selin Cerav-Erbas, Static priority scheduling of event-triggered real-time embedded systems., Formal Methods in System Design 30(1): 29-47 (2007)
Carles Pairot Gavalda, Pedro Garcia Lopez, Ruben Mondejar Andreu, Deploying Wide-Area Applications Is a Snap, IEEE Internet Computing , Volume 11 Issue 2, IEEE Educational Activities Department, March 2007
Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis, A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions., ARC 2007: 130-141
Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis, A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size., SAMOS 2007: 283-293
Carlos Dominguez, Houcine Hassan, Alfons Crespo, Real-Time Embedded Architecture for Pervasive Robots, IPC '07: Proceedings of the The 2007 International Conference on Intelligent Pervasive Computing, IEEE Computer Society, October 2007
Carlos García, Manuel Prieto, Francisco Tirado, Multigrid Smoothers on Multicore Architectures., PARCO 2007: 279-286
Carlos Morra, João M. P. Cardoso, Jürgen Becker, Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements., IPDPS 2007: 1-8
Carmen Martínez, Ramón Beivide, Ernst M. Gabidulin, Perfect Codes for Metrics Induced by Circulant Graphs., IEEE Transactions on Information Theory 53(9): 3042-3052 (2007)
Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy, A hardware/software framework for supporting transactional memory in a MPSoC environment, SIGARCH Computer Architecture News , Volume 35 Issue 1, ACM, March 2007
Chang-Hua Wu, Weihua Sheng, Ying Zhang, Mobile Sensor Networks Self Localization based on Multi-dimensional Scaling., ICRA 2007: 4038-4043
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Grasso Bronson, Jared Casper, Christos Kozyrakis, Kunle Olukotun, An effective hybrid transactional memory system with strong isolation guarantees., ISCA 2007: 69-80
Chris Bleakley, Tom Clerckx, Harald Devos, Matthias Grumer, Alex Janek, Ulrich Kremer, Christian W. Probst, Phillip Stanley-Marbell, Christian Steger, Vasanth Venkatachalam, Manuel Wendt, 07041 Working Group - Towards Interfaces for Integrated Performance and Power Analysis and Simulation., Power-aware Computing Systems 2007
Christian Haubelt, Joachim Falk, Joachim Keinert, Thomas Schlichter, Martin Streubühr, Andreas Deyhle, Andreas Hadert, Jürgen Teich, A SystemC-based design methodology for digital signal processing systems, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Christian Pilato, Gianluca Palermo, Antonino Tumeo, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi, Fitness inheritance in evolutionary and multi-objective high-level synthesis., IEEE Congress on Evolutionary Computation 2007: 3459-3466
Christian W. Probst, Ulrich Kremer, Luca Benini, Peter Schelkens, Power-aware computing systems., IJES 3(1/2): 3-7 (2007)
Christine Rochange, 7th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis Pisa Italy July 3 2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI) Schloss Dagstuhl Germany 2007
Christine Rochange, WCET 2007 Abstracts Collection - 7th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis., WCET 2007
Christophe Alias, Fabrice Baray, Alain Darte, Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose., LCTES 2007: 73-82
Christophe Dubach, John Cavazos, Björn Franke, Grigori Fursin, Michael F. P. O'Boyle, Olivier Temam, Fast compiler optimisation evaluation using code-feature based performance prediction., Conf. Computing Frontiers 2007: 131-142
Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle, Microarchitectural Design Space Exploration Using an Architecture-Centric Approach., MICRO 2007: 262-271
Christophe Poucet, Stylianos Mamagkakis, David Atienza, Francky Catthoor, Systematic intermediate sequence removal for reduced memory accesses., SCOPES 2007: 51-60
Christos Baloukas, Lazaros Papadopoulos, Stylianos Mamagkakis, Dimitrios Soudris, Component Based Library Implementation of Abstract Data Types for Resource Management Customization of Embedded Systems., ESTImedia 2007: 99-104
Christos Koulamas, Aggeliki S. Prayati, George Papadopoulos, A framework for the implementation of adaptive streaming systems., WMuNeP 2007: 23-26
Christos-S Bouganis, Iosifina Pournara, Peter Y. K. Cheung, Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications., FPL 2007: 196-201
Clemens Moser, Davide Brunelli, Lothar Thiele, Luca Benini, Real-time scheduling for energy harvesting sensor nodes., Real-Time Systems 37(3): 233-260 (2007)
Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini, Adaptive power management in energy harvesting systems., DATE 2007: 773-778
Colby Ranger, Ramanan Raghuraman, Arun Penmetsa, Gary R. Bradski, Christos Kozyrakis, Evaluating MapReduce for Multi-core and Multiprocessor Systems., HPCA 2007: 13-24
Cosmin E. Oancea, Alan Mycroft, A Lightweight Model for Software Thread-Level Speculation (TLS)., PACT 2007: 419
Crispín Gómez Requena, Francisco Gilabert, María Engracia Gómez, Pedro López, José Duato, Deterministic versus Adaptive Routing in Fat-Trees., IPDPS 2007: 1-8
Crispín Gómez Requena, María Engracia Gómez, Pedro López, José Duato, An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks., ISPA 2007: 509-522
Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio, TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs., DFT 2007: 87-95
Cristiana Bolchini, Carlo Curino, Elisa Quintarelli, Fabio A. Schreiber, Letizia Tanca, A data-oriented survey of context models., SIGMOD Record 36(4): 19-26 (2007)
Cristiana Bolchini, Carlo Curino, Giorgio Orsi, Elisa Quintarelli, Fabio A. Schreiber, Letizia Tanca, CADD: A Tool for Context Modeling and Data Tailoring., MDM 2007: 221-223
Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio, SEU mitigation for sram-based fpgas through dynamic partial reconfiguration., ACM Great Lakes Symposium on VLSI 2007: 55-60
Cristiana Bolchini, Elisa Quintarelli, Rosalba Rossato, Relational Data Tailoring Through View Composition., ER 2007: 149-164
Cristiana Bolchini, Elisa Quintarelli, Rosalba Rossato, Letizia Tanca, Using Context for the Extraction of Relational Views., CONTEXT 2007: 108-121
Cristiana Bolchini, Fabio A. Schreiber, Letizia Tanca, A methodology for a Very Small Data Base design., Inf. Syst. 32(1): 61-82 (2007)
Cristiana Bolchini, Fabio Salice, Marco D. Santambrogio, Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs., ERSA 2007: 199-202
Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) 26-28 September 2007 Rome Italy., IEEE Computer Society 2007
Cyprian Grassmann, Mathias Richter, Mirko Sauermann, Mapping the physical layer of radio standards to multiprocessor architectures., DATE 2007: 1412-1417
Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin, A design flow dedicated to multi-mode architectures for DSP applications., ICCAD 2007: 604-611
D. Gao, Y. Wang, H. Hindi, M. Do, Decompose Document Image Using Integer Linear Programming, ICDAR '07: Proceedings of the Ninth International Conference on Document Analysis and Recognition - Volume 01 , Volume 01, IEEE Computer Society, September 2007
Damien Sauveron, Constantinos Markantonakis, Angelos Bilas, Jean-Jacques Quisquater, Information Security Theory and Practices. Smart Cards Mobile and Ubiquitous Computing Systems First IFIP TC6 / WG 8.8 / WG 11.2 International Workshop WISTP 2007 Heraklion Crete Greece May 9-11 2007 Proceedings, Springer 2007
Dan Tsafrir, Keren Ouaknine, Dror G. Feitelson, Reducing Performance Evaluation Sensitivity and Variability by Input Shaking., MASCOTS 2007: 231-237
Dan Tsafrir, Yoav Etsion, Dror G. Feitelson, Backfilling Using System-Generated Predictions Rather than User Runtime Estimates., IEEE Trans. Parallel Distrib. Syst. 18(6): 789-803 (2007)
Dan Tsafrir, Yoav Etsion, Dror G. Feitelson, Secretly monopolizing the CPU without superuser privileges, SS'07: Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium, USENIX Association, August 2007
Daniel Díaz, Xoán C. Pardo, María J. Martín, Patricia González, Gabriel Rodríguez, CPPC-G: Fault-Tolerant Applications on the Grid., PPAM 2007: 852-859
Daniel Grund, Sebastian Hack, A Fast Cutting-Plane Algorithm for Optimal Coalescing., CC 2007: 111-125
Daniel Jiménez-González, Xavier Martorell, Alex Ramírez, Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications., ISPASS 2007: 210-219
Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam, Implementing Signatures for Transactional Memory, MICRO '07: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, IEEE Computer Society, December 2007
David Atienza, Christos Baloukas, Lazaros Papadopoulos, Christophe Poucet, Stylianos Mamagkakis, José Ignacio Hidalgo, Francky Catthoor, Dimitrios Soudris, Juan Lanchares, Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation., SCOPES 2007: 31-40
David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, HW-SW emulation framework for temperature-aware design in MPSoCs., ACM Trans. Design Autom. Electr. Syst. 12(3): (2007)
David B. Thomas, Jacob A. Bower, Wayne Luk, Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations., ASAP 2007: 168-173
David B. Thomas, Wayne Luk, High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices., VLSI Signal Processing 47(1): 77-92 (2007)
David B. Thomas, Wayne Luk, Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
David B. Thomas, Wayne Luk, Michael Stumpf, Reconfigurable Hardware Acceleration of Canonical Graph Labelling., ARC 2007: 302-313
David B. Thomas, Wayne Luk, Philip Heng Wai Leong, John D. Villasenor, Gaussian random number generators., ACM Comput. Surv. 39(4): (2007)
David Chi-Leung Wong, Albert Cohen, María Jesús Garzarán, Christian Lengauer, Samuel P. Midkiff, 07361 Abstracts Collection -- Programming Models for Ubiquitous Parallelism., Programming Models for Ubiquitous Parallelism 2007
David Chi-Leung Wong, Albert Cohen, María Jesús Garzarán, Christian Lengauer, Samuel P. Midkiff, 07361 Introduction -- Programming Models for Ubiquitous Parallelism., Programming Models for Ubiquitous Parallelism 2007
David E. Singh, Alejandro Miguel, Félix García, Jesús Carretero, MASIPE: A Tool Based on Mobile Agents for Monitoring Parallel Environments., PPAM 2007: 870-879
David E. Singh, Florin Isaila, Alejandro Calderón, Félix García, Jesús Carretero, Multiple-Phase Collective I/O Technique for Improving Data Access Locality., PDP 2007: 534-542
David E. Singh, Florin Isaila, Juan Carlos Pichel, Jesús Carretero, A collective I/O implementation based on Inspector-Executor paradigm., PDPTA 2007: 683-689
David Gregg, Colm McSweeney, Ciarán McElroy, Fergal Connor, Séamas McGettrick, David Moloney, Dermot Geraghty, FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory., FPL 2007: 786-791
David I. August, Jonathan Chang, Sylvain Girbal, Daniel Gracia Pérez, Gilles Mouchard, David A. Penry, Olivier Temam, Neil Vachharajani, UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development., Computer Architecture Letters 6(2): 45-48 (2007)
David J. Pearce, Matthew Webster, Robert Berry, Paul H. J. Kelly, Profiling with AspectJ., Softw. Pract. Exper. 37(7): 747-777 (2007)
David J. Pearce, Paul H. J. Kelly, Chris Hankin, Efficient field-sensitive pointer analysis of C., ACM Trans. Program. Lang. Syst. 30(1): (2007)
David R Lester, Topology in PVS: continuous mathematics with applications, AFM '07: Proceedings of the second workshop on Automated formal methods, ACM, November 2007
David Talby, Dror G. Feitelson, Adi Raveh, A Co-Plot analysis of logs and models of parallel workloads., ACM Trans. Model. Comput. Simul. 17(3): (2007)
David Verstraeten, Benjamin Schrauwen, Dirk Stroobandt, Adapting reservoir states to get Gaussian distributions., ESANN 2007: 495-500
David Verstraeten, Benjamin Schrauwen, Michiel D'Haene, Dirk Stroobandt, An experimental unification of reservoir computing methods., Neural Networks 20(3): 391-403 (2007)
Davide Bertozzi, Shashi Kumar, Maurizio Palesi, Networks-on-Chip, Networks-on-Chip, Hindawi Publishing Corporation, April 2007
Davy Genbrugge, Lieven Eeckhout, Statistical simulation of chip multiprocessors running multi-program workloads., ICCD 2007: 464-471
Demid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis, Instruction-Level Fault Tolerance Configurability., ICSAMOS 2007: 110-117
Denis Krivitski, Assaf Schuster, Ran Wolff, A Local Facility Location Algorithm for Large-scale Distributed Systems., J. Grid Comput. 5(4): 361-378 (2007)
Dennis Vermoen, Marc F. Witteman, Georgi Gaydadjiev, Reverse Engineering Java Card Applets Using Power Analysis., WISTP 2007: 138-149
Diego Andrade, Basilio B. Fraguela, Ramon Doallo, Precise automatable analytical modeling of the cache behavior of codes with indirections., TACO 4(3): (2007)
Diego Andrade, Manuel Arenaz, Basilio B. Fraguela, Juan Touriño, Ramon Doallo, Automated and accurate cache behavior analysis for codes with irregular access patterns., Concurrency and Computation: Practice and Experience 19(18): 2407-2423 (2007)
Diego R. Llanos, Review of “Grid Computing Security by Anirban Chakrabarti”, Springer, 2007, $69.95, ISBN: 3540444920, Queue , Volume 5 Issue 6, ACM, September 2007
Diego R. Llanos Ferraris, David Orden, Belén Palop, New Scheduling Strategies for Randomized Incremental Algorithms in the Context of Speculative Parallelization., IEEE Trans. Computers 56(6): 839-852 (2007)
Diego R. Martínez, Vicente Blanco Pérez, Marcos Boullón, José Carlos Cabaleiro, Casiano Rodríguez, Francisco F. Rivera, Software Tools for Performance Modeling of Parallel Programs., IPDPS 2007: 1-8
Diego R. Martínez, Vicente Blanco, Marcos Boullón, José Carlos Cabaleiro, Tomás F. Pena, Analytical Performance Models of Parallel Programs in Clusters., PARCO 2007: 99-106
Diego Sevilla, José M. García, Antonio F. Gómez-Skarmeta, Aspect-Oriented Programing Techniques to support Distribution Fault Tolerance and Load Balancing in the CORBA-LC Component Model., NCA 2007: 195-204
Diego Sevilla, José M. García, Antonio Gómez, Using AOP to Automatically Provide Distribution Fault Tolerance and Load Balancing to the CORBA-LC Component Model., PARCO 2007: 347-354
Dietmar Ebner, Florian Brandner, Andreas Krall, Leveraging Predicated Execution for Multimedia Processing., ESTImedia 2007: 85-90
Dirk Koch, Christian Haubelt, Jürgen Teich, Efficient hardware checkpointing: concepts overhead analysis and implementation., FPGA 2007: 188-196
Dirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich, Modeling and Synthesis of Hardware-Software Morphing., ISCAS 2007: 2746-2749
Dmitrijs Zaparanuks, Milan Jovic, Matthias Hauswirth, The potential of speculative class-loading., PPPJ 2007: 209-214
Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque, Adaptive L2 Cache for Chip Multiprocessors., Euro-Par Workshops 2007: 28-37
Dominique Chanet, Bjorn De Sutter, Bruno De Bus, Ludo Van Put, Koen De Bosschere, Automated reduction of the memory footprint of the Linux kernel., ACM Trans. Embedded Comput. Syst. 6(4): (2007)
Dries Buytaert, Andy Georges, Michael Hind, Matthew Arnold, Lieven Eeckhout, Koen De Bosschere, Using hpm-sampling to drive dynamic compilation., OOPSLA 2007: 553-568
Dries Buytaert, Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, GCH: Hints for Triggering Garbage Collections., T. HiPEAC 1: 74-94 (2007)
Dror Feitelson, Teaching TCP/IP Hands-On, IEEE Distributed Systems Online , Volume 8 Issue 11, IEEE Educational Activities Department, November 2007
Dror G. Feitelson, Locality of sampling and diversity in parallel system workloads., ICS 2007: 53-63
Dror G. Feitelson, Introduction., Commun. ACM 50(11): 24-26 (2007)
Dror G. Feitelson, Asimov's Laws of Robotics Applied to Software., IEEE Software 24(4): 111-112 (2007)
Dror G. Feitelson, Tokunbo O. S. Adeshiyan, Daniel Balasubramanian, Yoav Etsion, Gabor Madl, Esteban Osses, Sameer Singh, Karlkim Suwanmongkol, Minhui Xie, Stephen R. Schach, Fine-grain analysis of common coupling and its application to a Linux case study., Journal of Systems and Software 80(8): 1239-1255 (2007)
E. Moyano-Ávila, F. J. Quiles, L. Orozco-Barbosa, Development and evaluation of high-performance decorrelation algorithms for the nonalternating 3D wavelet transform, EURASIP Journal on Applied Signal Processing , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Edi Shmueli, Dror G. Feitelson, Uncovering the Effect of System Performance on User Behavior from Traces of Parallel Systems., MASCOTS 2007: 274-280
Eduard Ayguadé, Gerald Baumgartner, J. Ramanujam, P. Sadayappan, Languages and Compilers for Parallel Computing: 18th International Workshop, LCPC 2005Hawthorne, NY, USA, October 20-22, 2005Revised Selected Papers (Lecture Notes in Computer Science), Languages and Compilers for Parallel Computing: 18th International Workshop, LCPC 2005Hawthorne, NY, USA, October 20-22, 2005Revised Selected Papers (Lecture Notes in Computer Science), Springer-Verlag New York, Inc., February 2007
Eduard Ayguadé, Matthias S. Müller, Special Issue on OpenMP - Guest Editors' Introduction., International Journal of Parallel Programming 35(4): 331-333 (2007)
Eduard Ayguadé, Matthias S. Müller, Introduction., International Journal of Parallel Programming 35(5): 437-439 (2007)
Eduard Ayguadé, Nawal Copty, Alejandro Duran, Jay Hoeflinger, Yuan Lin, Federico Massaioli, Ernesto Su, Priya Unnikrishnan, Guansong Zhang, A Proposal for Task Parallelism in OpenMP., IWOMP 2007: 1-12
Eduard Ayguade, Alejandro Duran, Jay Hoeflinger, Federico Massaioli, Xavier Teruel, An Experimental Evaluation of the New OpenMP Tasking Model., LCPC 2007: 63-77
Edwin Steiner, Andreas Krall, Christian Thalinger, Adaptive inlining and on-stack replacement in the CACAO virtual machine., PPPJ 2007: 221-226
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna, Configurable implementation of parallel memory based real-time video downscaler., Microprocessors and Microsystems 31(5): 283-292 (2007)
Eladio Gutierrez, Sergio Romero, Maria A. Trenas, Emilio L. Zapata, Simulation of quantum gates on a novel GPU architecture, ISTASC'07: Proceedings of the 7th Conference on 7th WSEAS International Conference on Systems Theory and Scientific Computation - Volume 7 , Volume 7, World Scientific and Engineering Academy and Society (WSEAS), August 2007
Electra Tamani, Paraskevas Evripidou, A Pragmatic Methodology to Web Service Discovery., ICWS 2007: 1168-1171
Electra Tamani, Paraskevas Evripidou, Combining Pragmatics and Intelligence in Semantic Web Service Discovery., OTM Workshops (2) 2007: 824-833
Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis, The Molen compiler for reconfigurable processors., ACM Trans. Embedded Comput. Syst. 6(1): (2007)
Eli Pozniansky, Assaf Schuster, MultiRace: efficient on-the-fly data race detection in multithreaded C++ programs., Concurrency and Computation: Practice and Experience 19(3): 327-340 (2007)
Elias Athanasopoulos, Mema Roussopoulos, Kostas G. Anagnostakis, Evangelos P. Markatos, GAS: Overloading a File Sharing Network as an Anonymizing System., IWSEC 2007: 365-379
Elisabetta Farella, Luca Benini, Bruno Riccò, Andrea Acquaviva, MOCA: a low-power, low-cost motion capture system based on integrated accelerometers, Advances in Multimedia , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Emiliano Dolif, Michele Lombardi, Martino Ruggiero, Michela Milano, Luca Benini, Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip., EMSOFT 2007: 47-56
Emilio J. Padrón, Margarita Amor, Montserrat Bóo, Ramon Doallo, A Hierarchical Radiosity Method with Scene Distribution., PDP 2007: 134-138
Emre Özer, Alastair Reid, Stuart Biles, Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor., SBAC-PAD 2007: 37-44
Emre Özer, Stuart Biles, Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor., Asia-Pacific Computer Systems Architecture Conference 2007: 376-386
Enno Lübbers, Marco Platzner, ReconOS: An RTOS supporting Hard- and Software Threads., FPL 2007: 441-446
Enric Jaén Villoldo, Joan Serrat-Fernandez, Emilio Luque, Improving Web Services Interoperability with Binding Extensions., ICWS 2007: 873-879
Enric Morancho, José María Llabería, Àngel Olivé, On reducing energy-consumption by late-inserting instructions into the issue queue., ISLPED 2007: 371-374
Enric Morancho, José María Llabería, Àngel Olivé, A comparison of two policies for issuing instructions speculatively., Journal of Systems Architecture 53(4): 170-183 (2007)
Eric A. Antonelo, Benjamin Schrauwen, Xavier Dutoit, Dirk Stroobandt, Marnix Nuttin, Event Detection and Localization in Mobile Robot Navigation Using Reservoir Computing., ICANN (2) 2007: 660-669
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai, PROToFLEX: FPGA-accelerated Hybrid Functional Simulator., IPDPS 2007: 1-6
Erik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi, Parallel Computing with FPGAs - Concepts and Applications., PARCO 2007: 739-740
Ernie Chan, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn, Supermatrix out-of-order scheduling of matrix operations for SMP and multi-core architectures., SPAA 2007: 116-125
Ernie Chan, Field G. Van Zee, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn, Satisfying your dependencies with SuperMatrix., CLUSTER 2007: 91-99
Erno Salminen, Ari Kulmala, Timo D. Hämäläinen, On network-on-chip comparison., DSD 2007: 503-510
Erno Salminen, Tero Kangas, Vesa Lahtinen, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen, Benchmarking mesh and hierarchical bus networks in system-on-chip context., Journal of Systems Architecture 53(8): 477-488 (2007)
Eun Jung Kim, Ki Hwan Yum, Chita R. Das, Mazin S. Yousif, José Duato, Exploring IBA Design Space for Improved Performance., IEEE Trans. Parallel Distrib. Syst. 18(4): 498-510 (2007)
Evangelos Koukis, Nectarios Koziris, Efficient Block Device Sharing over Myrinet with Memory Bypass., IPDPS 2007: 1-10
Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny, Routing table minimization for irregular mesh NoCs., DATE 2007: 942-947
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny, The Power of Priority: NoC Based Distributed Cache Coherency., NOCS 2007: 117-126
Ezequiel Herruzo, Emilio L. Zapata, Oscar G. Plata, Maximum and Sorted Cache Occupation Using Array Padding., ICSAMOS 2007: 178-185
Ezequiel Herruzo, Guillermo Ruíz, J. Ignacio Benavides, Oscar G. Plata, A New Parallel Sorting Algorithm based on Odd-Even Mergesort., PDP 2007: 18-22
Ezequiel Herruzo, J. Ignacio Benavides, Ricardo Quislant, Emilio L. Zapata, Oscar Plata, Simulating a Reconfigurable Cache System for Teaching Purposes, MSE '07: Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education, IEEE Computer Society, June 2007
Félix García Carballeira, Jesús Carretero, Alejandro Calderón, José Daniel García, Luis Miguel Sánchez, A global and parallel file system for grids., Future Generation Comp. Syst. 23(1): 116-122 (2007)
F. Castanedo, M. A. Patricio, J. Garcia, J. M. Molina, Bottom-up/top-down coordination in a multiagent visual sensor network, AVSS '07: Proceedings of the 2007 IEEE Conference on Advanced Video and Signal Based Surveillance - Volume 00 , Volume 00, IEEE Computer Society, September 2007
F. Cedo, Ana Cortés, Ana Ripoll, Miquel A. Senar, Emilio Luque, The Convergence of Realistic Distributed Load-Balancing Algorithms., Theory Comput. Syst. 41(4): 609-618 (2007)
F. Dahlgren, Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms, PATMOS '07: Proceedings of the 17th international workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, September 2007
F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera, Hardware support for adaptive tessellation of Bézier surfaces based on local tests., Journal of Systems Architecture 53(4): 233-250 (2007)
F. Lin, H. Ying, R. D. MacArthur, J. A. Cohn, D. Barth-Jones, L. R. Crane, Decision making in fuzzy discrete event systems, Information Sciences: an International Journal , Volume 177 Issue 18, Elsevier Science Inc., September 2007
Fabian Nowak, Rainer Buchty, Wolfgang Karl, A Run-time Reconfigurable Cache Architecture., PARCO 2007: 757-766
Fabio Garzia, Claudio Brunelli, Andrea Ferro, Jari Nurmi, Implementation of a 2D low-pass image filtering algorithm on a reconfigurable device., ReCoSoC 2007: 166-170
Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo, Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs., IESS 2007: 179-192
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo, An Evolutionary Approach to Area-Time Optimization of FPGA designs., ICSAMOS 2007: 145-152
Fabrizio Petrini, Gordon Fossum, Juan Fernández, Ana Lucia Varbanescu, Michael Kistler, Michael Perrone, Multicore Surprises: Lessons Learned from Optimizing Sweep3D on the Cell Broadband Engine., IPDPS 2007: 1-10
Fadia Nemer, Hugues Cassé, Pascal Sainrat, Ali Awada, Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis., SIES 2007: 25-32
Faith Ellen, Panagiota Fatourou, Eric Ruppert, The Space Complexity of Unbounded Timestamps., DISC 2007: 223-237
Faith Ellen, Panagiota Fatourou, Eric Ruppert, Time lower bounds for implementations of multi-writer snapshots., J. ACM 54(6): (2007)
Farrukh Nadeem, Radu Prodan, Thomas Fahringer, Optimizing Performance of Automatic Training Phase for Application Performance Prediction in the Grid., HPCC 2007: 309-321
Faruk Bagci, Holger Schick, Jan Petzold, Wolfgang Trumler, Theo Ungerer, The reflective mobile agent paradigm implemented in a smart office environment., Personal and Ubiquitous Computing 11(1): 11-19 (2007)
Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli, Interactive presentation: Improving the fault tolerance of nanometric PLA designs., DATE 2007: 570-575
Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo, Luca Benini, A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs., IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 421-434 (2007)
Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, R. Ramanarayanan, Balaji Vaidyanathan, A Process Scheduler-Based Approach to NoC Power Management., VLSI Design 2007: 77-82
Filip Blagojevic, Alexandros Stamatakis, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, RAxML-Cell: Parallel Phylogenetic Tree Inference on the Cell Broadband Engine., IPDPS 2007: 1-10
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexandros Stamatakis, Christos D. Antonopoulos, Dynamic multigrain parallelization on the cell broadband engine., PPOPP 2007: 90-100
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexandros Stamatakis, Christos D. Antonopoulos, Matthew Curtis-Maury, Runtime scheduling of dynamic parallelism on accelerator-based multi-core systems., Parallel Computing 33(10-11): 700-719 (2007)
Filipa Duarte, Stephan Wong, A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies., ASAP 2007: 397-402
Florent Bouchez, Alain Darte, Fabrice Rastello, On the Complexity of Register Coalescing., CGO 2007: 102-114
Florent Bouchez, Alain Darte, Fabrice Rastello, On the complexity of spill everywhere under SSA form., LCTES 2007: 103-112
Florian Brandner, Dietmar Ebner, Andreas Krall, Compiler generation from structural architecture descriptions., CASES 2007: 13-22
Florian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, MORPHEUS: Heterogeneous Reconfigurable Computing., FPL 2007: 409-414
Frédéric Gruau, Christine Eisenbeis, Programming self developing blob machines for spatial computing.., Computing Media and Languages for Space-Oriented Computation 2007
Francesc Giné, Francesc Solsona, Mauricio Hanzich, Porfidio Hernández, Emilio Luque, Cooperating CoScheduling: A Coscheduling Proposal Aimed at Non-Dedicated Heterogeneous NOWs., J. Comput. Sci. Technol. 22(5): 695-710 (2007)
Francesc Guim, Ivan Rodero, Julita Corbalán, Jesús Labarta, Ariel Oleksiak, Tomasz Kuczynski, Dawid Szejnfeld, Jarek Nabrzyski, Uniform job monitoring in the HPC-Europa project: data model API and services., IJWGS 3(3): 333-353 (2007)
Francesc Guim, Julita Corbalán, Jesús Labarta, Modeling the Impact of Resource Sharing in Backfilling Policies using the Alvio Simulator., MASCOTS 2007: 145-150
Francesc Guim, Julita Corbalán, Jesús Labarta, Prediction f Based Models for Evaluating Backfilling Scheduling Policies., PDCAT 2007: 9-17
Francesco D'Ascoli, Francesco Iozzi, Corrado Marino, Massimiliano Melani, Marco Tonarelli, Luca Fanucci, A. Giambastiani, A. Rocchi, Marco De Marinis, Low-g accelerometer fast prototyping for automotive applications., DATE 2007: 486-491
Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini, Pol Marchal, Mirko Loghi, Massimo Poncino, Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support., IEEE Trans. Computers 56(5): 606-621 (2007)
Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ie, A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies., ICSAMOS 2007: 209-214
Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar, Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits., DFT 2007: 508-516
Francisco Delicado, Pedro Cuenca, Luis Orozco-Barbosa, Developing a QoS framework for media streaming over TDMA/TDD wireless networks., IJWMC 2(2/3): 120-131 (2007)
Francisco Delicado, Pedro Cuenca, Luis Orozco-Barbosa, Hierarchical MPEG-4 video transmission over TDMA/TDD wireless LAN., Telecommunication Systems 36(1-3): 129-139 (2007)
Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero, On the Problem of Minimizing Workload Execution Time in SMT Processors., ICSAMOS 2007: 66-73
Francisco Javier Ridruejo Perez, Javier Navaridas, José Miguel-Alonso, Cruz Izu, Realistic Evaluation of Interconnection Network Performance at High Loads., PDCAT 2007: 97-104
Francisco Javier Ridruejo Perez, José Miguel-Alonso, Javier Navaridas, Concepts and components of full-system simulation of distributed memory parallel computers., HPDC 2007: 225-226
Francisco José Alfaro, José L. Sánchez, M. Menduiña, José Duato, A Formal Model to Manage the InfiniBand Arbitration Tables Providing QoS., IEEE Trans. Computers 56(8): 1024-1039 (2007)
Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev, Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array., ARC 2007: 1-13
Frederic Worm, Patrick Thiran, Paolo Ienne, Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs., ISQED 2007: 861-866
Frederik Vandeputte, Lieven Eeckhout, Koen De Bosschere, Exploiting program phase behavior for energy reduction on multi-configuration processors., Journal of Systems Architecture 53(8): 489-500 (2007)
Fredrik Dahlgren, Partial Continuous Functions and Admissible Domain Representations., J. Log. Comput. 17(6): 1063-1081 (2007)
Gabriel Rodríguez, Patricia González, María J. Martín, Juan Touriño, Enhancing Fault-Tolerance of Large-Scale MPI Scientific Applications., PaCT 2007: 153-161
Gala Yadgar, Michael Factor, Assaf Schuster, Karma: know-it-all replacement for a multilevel cache, FAST '07: Proceedings of the 5th USENIX conference on File and Storage Technologies, USENIX Association, February 2007
Gaspar Mora, Pedro Javier García, Jose Flich, José Duato, RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management., ICPP 2007: 74
George A. Constantinides, Special issue on Field-Programmable Technology., J. Real-Time Image Processing 2(4): 177-178 (2007)
George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis, Approaching Ideal NoC Latency with Pre-Configured Routes., NOCS 2007: 153-162
Georges G. E. Gielen, Donatella Sciuto, Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design Automation and Test in Europe Conference]., IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 405-407 (2007)
Georgios I. Goumas, Nikolaos Drosinos, Vasileios Karakasis, Nectarios Koziris, Coarse-grain Parallel Execution for 2-dimensional PDE Problems., IPDPS 2007: 1-8
Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Cache replacement based on reuse-distance prediction., ICCD 2007: 245-250
Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras, Applying Decay to Reduce Dynamic Power in Set-Associative Caches., HiPEAC 2007: 38-53
Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Philip K. F. Hölzenspies, Marcel D. van de Burgwal, Paul M. Heysters, The Chameleon architecture for streaming DSP applications, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Gerardo Fernández-Escribano, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, Reducing Motion Estimation Complexity in MPEG-2 TO H.264 Transcoding., ICME 2007: 440-443
Gerardo Fernández-Escribano, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, A first approach to speeding-up the inter mode selection in MPEG-2/H.264 transcoders using machine learning., Multimedia Tools Appl. 35(2): 225-240 (2007)
Gerardo Fernández-Escribano, Jens Bialkowski, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, André Kaup, H.263 to H.264 Transconding using Data Mining., ICIP (4) 2007: 81-84
Giacomo Paci, Francesco Poletti, Luca Benini, Paul Marchal, Exploring temperature-aware design in low-power MPSoCs., IJES 3(1/2): 43-51 (2007)
Giacomo Paci, Paul Marchal, Luca Benini, Exploration of Low Power Adders for a SIMD Data Path., ASP-DAC 2007: 914-919
Gianluca Palermo, Cristina Silvano, Giovanni Mariani, Riccardo Locatelli, Marcello Coppola, Application-Specific Topology Design Customization for STNoC., DSD 2007: 547-550
Gianluca Palermo, Giovanni Mariani, Cristina Silvano, Riccardo Locatelli, Marcello Coppola, Mapping and Topology Customization Approaches for Application-Specific STNoC Designs., ASAP 2007: 61-68
Gianluca Palermo, Giovanni Mariani, Cristina Silvano, Riccardo Locatelli, Marcello Coppola, A topology design customization approach for STNoC, Nano-Net '07: Proceedings of the 2nd international conference on Nano-Networks, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), September 2007
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos, Sorter Based Permutation Units for Media-Enhanced Microprocessors., IEEE Trans. VLSI Syst. 15(6): 711-715 (2007)
Giovanni Agosta, Francesco Bruschi, Donatella Sciuto, An efficient cost-based canonical form for Boolean matching., ACM Great Lakes Symposium on VLSI 2007: 445-448
Giovanni Agosta, Francesco Bruschi, Gerardo Pelosi, Donatella Sciuto, A Unified Approach to Canonical Form-based Boolean Matching., DAC 2007: 841-846
Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto, A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip., DFT 2007: 132-141
Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Multi-Accuracy Power and Performance Transaction-Level Modeling., IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1830-1842 (2007)
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Efficient design space exploration for application specific systems-on-a-chip., Journal of Systems Architecture 53(10): 733-750 (2007)
Giuseppe Gentile, Massimo Rovini, Luca Fanucci, Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes., DSD 2007: 369-375
Gregorio Bernabé, Ricardo Fernández, Jose M. García, Manuel E. Acacio, José González, An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology, Parallel Computing , Volume 33 Issue 1, Elsevier Science Publishers B. V., February 2007
Gregorio Bernabé, Ricardo Fernández, José M. García, Manuel E. Acacio, José González, An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology., Parallel Computing 33(1): 54-72 (2007)
Grigori Fursin, Albert Cohen, Michael F. P. O'Boyle, Olivier Temam, Quick and Practical Run-Time Evaluation of Multiple Program Optimizations., T. HiPEAC 1: 34-53 (2007)
Grigori Fursin, John Cavazos, Michael F. P. O'Boyle, Olivier Temam, MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization., HiPEAC 2007: 245-260
Grzegorz Danilewicz, Wojciech Kabacinski, Marek Michalski, Mariusz Zal, Wide-Sense Nonblocking Multiplane Baseline Switching Networks Composed of d d Switches., ICC 2007: 6386-6391
Guillaume Chelius, Antoine Fraboulet, Eric Fleury, Worldsens: a fast and accurate development framework for sensor network applications., SAC 2007: 222-226
Guillermo L. Taboada, Carlos Teijeiro, Juan Touriño, High Performance Java Remote Method Invocation for Parallel Computing on Clusters., ISCC 2007: 233-239
Guillermo L. Taboada, Juan Touriño, Ramon Doallo, High Performance Java Sockets for Parallel Computing on Clusters., IPDPS 2007: 1-8
Gulay Yalcin, Oguz Ergin, Using Tag-Match Comparators for Detecting Soft Errors., Computer Architecture Letters 6(2): 53-56 (2007)
Gunnar Brataas, Jacqueline Floch, Romain Rouvoy, Pyrros Bratskas, George A. Papadopoulos, A basis for performance property prediction of ubiquitous self-adapting systems, ESSPE '07: International workshop on Engineering of software services for pervasive environments: in conjunction with the 6th ESEC/FSE joint meeting, ACM, September 2007
Håkan Zeffer, Erik Hagersten, A case for low-complexity MP architectures., SC 2007: 19
Haakon Dybdahl, Per Stenström, Lasse Natvig, An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
Haakon Dybdahl, Per Stenström, An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors., HPCA 2007: 2-12
Hadas Kogan, Isaac Keslassy, Fundamental Complexity of Optical Systems., INFOCOM 2007: 2506-2510
Hadas Kogan, Isaac Keslassy, Optimal-Complexity Optical Router., INFOCOM 2007: 706-714
Hadda Cherroun, Paul Feautrier, An Exact Resource Constrained-Scheduler using Graph Coloring technique., AICCSA 2007: 554-561
Hagit Attiya, Faith Ellen, Panagiota Fatourou, The complexity of updating multi-writer snapshot objects., PODC 2007: 318-319
Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk, Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors., DAC 2007: 224-229
Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, ASIP architecture exploration for efficient IPSec encryption: A case study., ACM Trans. Embedded Comput. Syst. 6(2): (2007)
Hanno Scharwächter, Jonghee M. Yoon, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr, A code-generator generator for multi-output instructions., CODES+ISSS 2007: 131-136
Hans Vandierendonck, André Seznec, Fetch Gating Control Through Speculative Instruction Window Weighting., HiPEAC 2007: 120-135
Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat, By-passing the out-of-order execution pipeline to increase energy-efficiency., Conf. Computing Frontiers 2007: 97-104
Haohuan Fu, Oskar Mencer, Wayne Luk, Optimizing Logarithmic Arithmetic on FPGAs, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Harald Devos, Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt, Energy Scalability and the RESUME Scalable Video Codec., Power-aware Computing Systems 2007
Harald Devos, Kristof Beyls, Mark Christiaens, Jan M. Van Campenhout, Erik H. D'Hollander, Dirk Stroobandt, Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations., T. HiPEAC 1: 159-178 (2007)
Harald Servat, Cecilia Gonzalez, Xavier Aguilar, Daniel Cabrera, Daniel Jimenez, Drug Design on the Cell BroadBand Engine., PACT 2007: 425
Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, MTAP special issue on video transcoding to H.264., Multimedia Tools Appl. 35(2): 125-126 (2007)
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Austen McDonald, Chi Cao Minh, Woongki Baek, Christos Kozyrakis, Kunle Olukotun, A Scalable Non-blocking Approach to Transactional Memory., HPCA 2007: 97-108
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, Non Return Mobile Logic Family, IEEE Proc. Int. Symp. on Circuits and Syst. (ISCAS07), pp. 125-128
Heikki Orsila, Tero Kangas, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen, Automated memory-aware application distribution for Multi-processor System-on-Chips., Journal of Systems Architecture 53(11): 795-815 (2007)
Heiko Falk, Peter Marwedel, Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems Nice France April 20 2007, SCOPES 2007
Heiner Giefers, Marco Platzner, A Many-core Implementation based on the Reconfigurable Mesh Model., FPL 2007: 41-46
Heinz Wörn, Uwe Brinkschulte, Echtzeitsysteme: Grundlagen, Funktionsweisen, Anwendungen (eXamen.press), Echtzeitsysteme: Grundlagen, Funktionsweisen, Anwendungen (eXamen.press), Springer-Verlag New York, Inc., January 2007
Hendrik Eeckhaut, Harald Devos, Dirk Stroobandt, The Energy Scalability of Wavelet-Based Scalable Video Decoding., PATMOS 2007: 363-372
Hendrik Eeckhaut, Harald Devos, Peter Lambert, Davy De Schrijver, Wim Van Lancker, Vincent Nollet, Prabhat Avasare, Tom Clerckx, Fabio Verdicchio, Mark Christiaens, Peter Schelkens, Rik Van de Walle, , Scalable Wavelet-Based Video: From Server to Hardware-Accelerated Client., IEEE Transactions on Multimedia 9(7): 1508-1519 (2007)
Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, Dirk Stroobandt, FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder., SAMOS 2007: 169-178
Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt, Improving External Memory Access for Avalon Systems on Programmable Chips.., FPL 2007: 311-316
Henry Falconer, Paul H. J. Kelly, David M. Ingram, Michael R. Mellor, Tony Field, Olav Beckmann, A Declarative Framework for Analysis and Optimization., CC 2007: 218-232
Hildur Ólafsdóttir, Stéphanie Lanche, Tron A. Darvann, Nuno V. Hermann, Rasmus Larsen, Bjarne K. Ersbøll, Estanislao Oubel, Alejandro F. Frangi, Per Larsen, Chad A. Perlyn,, A Point-Wise Quantification of Asymmetry Using Deformation Fields: Application to the Study of the Crouzon Mouse Model., MICCAI (2) 2007: 452-459
Holger Blume, Georgi Gaydadjiev, C. John Glossner, Peter M. W. Knijnenburg, Proceedings of 2007 International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (IC-SAMOS 2007) Samos Greece July 16-19 2007, IEEE 2007
Hong Linh Truong, Schahram Dustdar, Thomas Fahringer, Performance metrics and ontologies for Grid workflows., Future Generation Comp. Syst. 23(6): 760-772 (2007)
Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier, Massively Parallel Processor Architectures: A Co-design Approach., ReCoSoC 2007: 61-68
Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich, Efficient control generation for mapping nested loop programs onto processor arrays., Journal of Systems Architecture 53(5-6): 300-309 (2007)
Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser, Model Transformations from a Data Parallel Formalism towards Synchronous Languages., FDL 2007: 255-260
Hugues Berry, Olivier Temam, Modeling self-developing biological neural networks., Neurocomputing 70(16-18): 2723-2734 (2007)
Humberto Calderon, Carlo Galuzzi, Georgi Gaydadjiev, Stamatis Vassiliadis, High-Bandwidth Address Generation Unit., SAMOS 2007: 251-262
Humberto Calderon, Georgi Gaydadjiev, Stamatis Vassiliadis, Reconfigurable Universal Adder., ASAP 2007: 186-191
Ian O'Connor, Faress Tissafi-Drissi, Frédéric Gaffiot, Joni Dambre, Michiel De Wilde, Jan Van Campenhout, D. Van Thourhout, Dirk Stroobandt, Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect., IEEE Trans. VLSI Syst. 15(8): 927-940 (2007)
Ian Watson, Chris C. Kirkham, Mikel Luján, A Study of a Transactional Parallel Routing Algorithm., PACT 2007: 388-398
Igor L. Markov, Louis Scheffer, Dirk Stroobandt, Special issue on System-Level Interconnect Prediction., Integration 40(4): 381 (2007)
Igor Loi, Federico Angiolini, Luca Benini, Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow, Nano-Net '07: Proceedings of the 2nd international conference on Nano-Networks, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), September 2007
Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli, Early wire characterization for predictable network-on-chip global interconnects., SLIP 2007: 57-64
Ilias Iliadis, Nikolaos Chrysos, Cyriel Minkenberg, Performance evaluation of the Data Vortex photonic switch., IEEE Journal on Selected Areas in Communications 25(S-6): 20-35 (2007)
Imran Rao, Nomica Imran, Salman Khan, Eui-nam Huh, TaeChoong Chung, Adaptive and Reconfigurable ResOurce Management for Wireless Sensors using Grid Technology., COMSWARE 2007
Ioannis Mavroidis, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem., IEEE International Workshop on Rapid System Prototyping 2007: 41-47
Ioannis Mavroidis, Ioannis Papaefstathiou, Dionisios Pnevmatikatos, A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos, A buffered crossbar-based chip interconnection framework supporting quality of service., ACM Great Lakes Symposium on VLSI 2007: 90-95
Ioannis Sarkas, Dimitrios Mavridis, Michail Papamichail, George Papadopoulos, Volterra Analysis Using Chebyshev Series., ISCAS 2007: 1931-1934
Iouliia Skliarova, Valery Sklyarov, Software/Configware Implementation of Combinatorial Algorithms., AICCSA 2007: 539-546
Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny, Access Regulation to Hot-Modules in Wormhole NoCs., NOCS 2007: 137-148
Ismo Hänninen, Jarmo Takala, Robust Adders Based on Quantum-Dot Cellular Automata., ASAP 2007: 391-396
Iván Díaz, Juan Touriño, Ramon Doallo, Towards Low-Latency Model-Oriented Distributed Systems Management., APNOMS 2007: 41-50
Ivan E. Villalon, Pedro Cuenca, Luis Orozco-Barbosa, Yongho Seok, Thierry Turletti, Cross-Layer Architecture for Adaptive Video Multicast Streaming Over Multirate Wireless LANs., IEEE Journal on Selected Areas in Communications 25(4): 699-711 (2007)
Ivan Pryanishnikov, Andreas Krall, R. Nigel Horspool, Compiler optimizations for processors with SIMD instructions., Softw. Pract. Exper. 37(1): 93-113 (2007)
Ivan Rodero, Francesc Guim, Julita Corbalán, Jesús Labarta, Design and Implementation of a General-Purpose API of Progress and Performance Indicators., PARCO 2007: 501-508
Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luca Benini, Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions., CODES+ISSS 2007: 217-226
Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson, Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology., T. HiPEAC 1: 239-258 (2007)
Izchak Sharfman, Assaf Schuster, Daniel Keren, Aggregate Threshold Queries in Sensor Networks., IPDPS 2007: 1-10
Izchak Sharfman, Assaf Schuster, Daniel Keren, A geometric approach to monitoring threshold functions over distributed data streams., ACM Trans. Database Syst. 32(4): (2007)
Jürgen Hofer, Thomas Fahringer, Grid Application Fault Diagnosis Using Wrapper Services and Machine Learning., ICSOC 2007: 233-244
Jürgen Hofer, Thomas Fahringer, The Otho Toolkit - Synthesizing tailor-made scientific grid application wrapper services., Multiagent and Grid Systems 3(3): 281-298 (2007)
Jürgen Teich, Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme)., it - Information Technology 49(3): 139- (2007)
Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet, A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation., ERSA 2007: 14-24
J. Gómez, Large vertex symmetric digraphs, Networks , Volume 50 Issue 4, Wiley-Interscience, December 2007
J. L. Martínez, Warnakulasuriya Anil Chandana Fernando, W. A. Rajitha Jayaruwan Weerakkody, J. Oliver, O. López, M. Martinez, M. Pérez, Pedro Cuenca, Francisco J. Quiles, Low-Complexity TTCM Based Distributed Video Coding Architecture., PSIVT 2007: 841-852
J. R. Cózar, N. Guil, J. M. González-Linares, E. L. Zapata, E. Izquierdo, Logotype detection to support semantic-based video annotation, Image Communication , Volume 22 Issue 7-8, Elsevier Science Inc., August 2007
Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis, Comparing memory systems for chip multiprocessors., ISCA 2007: 358-368
Jadwiga Indulska, Jianhua Ma, Laurence Tianruo Yang, Theo Ungerer, Jiannong Cao, Ubiquitous Intelligence and Computing 4th International Conference UIC 2007 Hong Kong China July 11-13 2007 Proceedings, Springer 2007
Jae Young Hur, Stephan Wong, Stamatis Vassiliadis, Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs., ARC 2007: 49-60
Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis, Systematic Customization of On-Chip Crossbar Interconnects., ARC 2007: 61-72
Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis, Customizing Reconfigurable On-Chip Crossbar Scheduler., ASAP 2007: 210-215
Jairo Balart, Marc González, Xavier Martorell, Eduard Ayguadé, Zehra Sura, Tong Chen, Tao Zhang, Kevin O'Brien, Kathryn M. O'Brien, A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor., LCPC 2007: 125-140
Jan Willem van den Brand, Calin Ciordas, Kees Goossens, Twan Basten, Congestion-controlled best-effort communication for networks-on-chip., DATE 2007: 948-953
Jan-David Mol, Dick H. J. Epema, Henk J. Sips, The Orchard Algorithm: Building Multicast Trees for P2P Video Multicasting Without Free-Riding., IEEE Transactions on Multimedia 9(8): 1593-1604 (2007)
Jangwoo Kim, Jared C. Smolens, Babak Falsafi, James C. Hoe, PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers., PRDC 2007: 298-305
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe, Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding., MICRO 2007: 197-209
Jari Heikkinen, Jarmo Takala, Effects of program compression., Journal of Systems Architecture 53(10): 679-688 (2007)
Jarmo Takala, Shuvra S. Bhattacharyya, Gang Qu, Editorial: embedded digital signal processing systems, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Jarmo Takala, Timo D. Hämäläinen, Andy D. Pimentel, Stamatis Vassiliadis, Editorial., Journal of Systems Architecture 53(8): 465 (2007)
Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala, Parallel Memory Architecture for TTA Processor., SAMOS 2007: 273-282
Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, Fuse: A Technique to Anticipate Failures due to Degradation in ALUs., IOLTS 2007: 15-22
Javier Navaridas, Francisco Javier Ridruejo Perez, José Miguel-Alonso, Evaluation of Interconnection Networks Using Full-System Simulators: Lessons Learned., Annual Simulation Symposium 2007: 155-162
Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero, FAME: FAirly MEasuring Multithreaded Architectures., PACT 2007: 305-316
Jay L. T. Cornwall, Paul H. J. Kelly, Phil Parsonage, Bruno Nicoletti, Explicit Dependence Metadata in an Active Visual Effects Library., LCPC 2007: 172-186
Jean Christophe Beyler, Philippe Clauss, Performance driven data cache prefetching in a dynamic software optimization system., ICS 2007: 202-209
Jens Gladigau, Christian Haubelt, Bernhard Niemann, Jürgen Teich, Mapping Actor-Oriented Models to TLM Architectures., FDL 2007: 128-133
Jens Knoop, George C. Necula, Wolf Zimmermann, Preface., Electr. Notes Theor. Comput. Sci. 176(3): 1-2 (2007)
Jeremy Singer, Gavin Brown, Ian Watson, John Cavazos, Intelligent selection of application-specific garbage collectors., ISMM 2007: 91-102
Jeremy Singer, Gavin Brown, Mikel Luján, Ian Watson, Towards intelligent analysis techniques for object pretenuring., PPPJ 2007: 203-208
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero, Microarchitectural Support for Speculative Register Renaming., IPDPS 2007: 1-10
Jesús Delicado, Francisco Delicado, Luis Orozco-Barbosa, Study of the IEEE 802.16 Contention-based Request Mechanism., PWC 2007: 87-98
Jialin Dou, Marcelo Cintra, A compiler cost model for speculative parallelization, Transactions on Architecture and Code Optimization (TACO) , Volume 4 Issue 2, ACM, June 2007
Jianwei Chen, Michel Dubois, Per Stenström, SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators., IEEE Micro 27(4): 34-48 (2007)
Jie Tao, Asadollah Shahbahrami, Ben Juurlink, Rainer Buchty, Wolfgang Karl, Stamatis Vassiliadis, Optimizing Cache Performance of the Discrete Wavelet Transform Using a Visualization Tool, ISM '07: Proceedings of the Ninth IEEE International Symposium on Multimedia, IEEE Computer Society, December 2007
Jie Tao, Kim D. Hoàng, Wolfgang Karl, CMP Cache Architecture and the OpenMP Performance., IWOMP 2007: 77-88
Jie Tao, Thomas Dressler, Wolfgang Karl, An Interactive Graphical Environment for Code Optimization., International Conference on Computational Science (2) 2007: 831-838
Jie Tao, Tobias Gaugler, Wolfgang Karl, A Profiling Tool for Detecting Cache-Critical Data Structures., Euro-Par 2007: 52-61
Jinfeng Huang, Jeroen Voeten, Henk Corporaal, Predictable real-time software synthesis., Real-Time Systems 36(3): 159-198 (2007)
Jinfeng Huang, Jeroen Voeten, Marcel A. Groothuis, Jan F. Broenink, Henk Corporaal, A model-driven design approach for mechatronic systems., ACSD 2007: 127-136
Jisheng Zhao, Matthew Horsnell, Ian Rogers, Andrew Dinn, Chris C. Kirkham, Ian Watson, Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation., Euro-Par 2007: 258-267
Jo Ebergen, Steve Furber, Arash Saifhashemi, Notes On Pulse Signaling, ASYNC '07: Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems, IEEE Computer Society, March 2007
João Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis, Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues., ARC 2007: 179-190
Joachim Keinert, Christian Haubelt, Jürgen Teich, Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow., ICSAMOS 2007: 161-168
Joachim Keinert, Joachim Falk, Christian Haubelt, Jürgen Teich, Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms., ESTImedia 2007: 113-118
Joan-Lluís Ferrer, Elvira Baydal, Antonio Robles, Pedro López, José Duato, Congestion Management in MINs through Marked and Validated Packets., PDP 2007: 254-261
Jochen Hollmann, Anders Ardö, Per Stenström, Effectiveness of caching in a distributed digital library system., Journal of Systems Architecture 53(7): 403-416 (2007)
Johan Cockx, Kristof Denolf, Bart Vanhoof, Richard Stahl, SPRINT: a tool to generate concurrent transaction-level models from sequential code, EURASIP Journal on Applied Signal Processing , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
John Cavazos, Grigori Fursin, Felix V. Agakov, Edwin V. Bonilla, Michael F. P. O'Boyle, Olivier Temam, Rapidly Selecting Good Compiler Optimizations using Performance Counters., CGO 2007: 185-197
John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steven S. Lumetta, Wen-mei W. Hwu, CIGAR: Application Partitioning for a CPU/Coprocessor Architecture., PACT 2007: 317-326
John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic, RAMP: Research Accelerator for Multiple Processors., IEEE Micro 27(2): 46-57 (2007)
Johnny Huynh, José Nelson Amaral, Paul Berube, Sid Ahmed Ali Touati, Evaluation of Offset Assignment Heuristics., HiPEAC 2007: 261-275
Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, On the feasibility of early routing capacitance estimation for FPGAs., FPL 2007: 234-239
Jonathan Rubin, Ian Watson, Investigating the Effectiveness of Applying Case-Based Reasoning to the Game of Texas Hold'em., FLAIRS Conference 2007: 417-422
JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally, Register pointer architecture for efficient embedded processors., DATE 2007: 600-605
Joonseok Park, Pedro C. Diniz, Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations., ARC 2007: 97-109
Jordi Guitart, David Carrera, Vicenç Beltran, Jordi Torres, Eduard Ayguadé, Designing an overload control strategy for secure e-commerce applications., Computer Networks 51(15): 4492-4510 (2007)
José Arturo González Gómez, Simulation as an intuition building tool for factory physics, SCSC: Proceedings of the 2007 summer computer simulation conference, Society for Computer Simulation International, July 2007
José A. de Holanda, Jecel Assumpcao, Denis F. Wolf, Eduardo Marques, João M. P. Cardoso, On Adapting Power Estimation Models for Embedded Soft-Core Processors., SIES 2007: 345-348
José C. Castillo, Teresa Olivares, Luis Orozco-Barbosa, Implementation of a rule-based routing protocol for wireless sensor networks., PM2HW2N 2007: 19-25
José Carlos Mouriño, María J. Martín, Patricia González, Ramon Doallo, Fault-tolerant solutions for a MPI compute intensive application., PDP 2007: 246-253
José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang, Designing a Posture Analysis System with Hardware Implementation., VLSI Signal Processing 47(1): 33-45 (2007)
José Ignacio Aliaga, Matthias Bollhöfer, Alberto F. Martín, Enrique S. Quintana-Ortí, Parallelization of Multilevel Preconditioners Constructed from Inverse-Based ILUs on Shared-Memory Multiprocessors., PARCO 2007: 287-294
José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest, Energy-aware compilation and hardware design for VLIW embedded systems., IJES 3(1/2): 73-82 (2007)
José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, Carlos A. López-Barrio, Thermal Characterization and Thermal Management in Processor-Based Systems., Power-aware Computing Systems 2007
José M. Badía, Peter Benner, Maribel Castillo, Heike Faßbender, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Strategies for Parallelizing the Solution of Rational Matrix Equations., PARCO 2007: 255-262
José M. Claver, G. León, High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs., FPL 2007: 629-632
José M. Claver, P. Agustí, G. León, Manel Canseco, A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA., FPL 2007: 567-570
José Manuel Velasco, David Atienza, Katzalin Olcoz, Francisco Tirado, Efficient Object Placement including Node Selection in a Distributed Virtual Machine., PARCO 2007: 509-516
José Villalón, Pedro Cuenca, Luis Orozco-Barbosa, On the capabilities of IEEE 802.11e for multimedia communications over heterogeneous 802.11/802.11e WLANs., Telecommunication Systems 36(1-3): 27-38 (2007)
Jose Flich, A. Mejia, Pedro López, José Duato, Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips., NOCS 2007: 183-194
Jose Flich, Andres Mejia, Pedro López, José Duato, Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips., NOCS 2007: 183-194
Jose Gonzalez-Mora, Fernando De la Torre, Rajesh Murthi, Nicolas Guil, Emilio L. Zapata, Bilinear Active Appearance Models., ICCV 2007: 1-8
Jose L. Ayala, Anya Apavatjrut, David Atienza, Marisa Lopez-Vallejo, Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems, IWIA '07: Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IEEE Computer Society, January 2007
Jose M. Camara, Miquel Moretó, Enrique Vallejo, Ramón Beivide, José Miguel-Alonso, Carmen Martínez, Javier Navaridas, Mixed-radix Twisted Torus Interconnection Networks., IPDPS 2007: 1-10
Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen, The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens)., it - Information Technology 49(3): 143- (2007)
Josep Domènech, Ana Pont, Julio Sahuquillo, José A. Gil, A user-focused evaluation of web prefetching algorithms., Computer Communications 30(10): 2213-2224 (2007)
Josep M. Pérez, Pieter Bellens, Rosa M. Badia, Jesús Labarta, CellSs: Making it easier to program the Cell Broadband Engine processor., IBM Journal of Research and Development 51(5): 593-604 (2007)
Juan A. Lorenzo, Julio L. Albín, Tomás F. Pena, Francisco F. Rivera, David E. Singh, An Inspector/Executor Based Strategy to Efficiently Parallelize N-Body Simulation Programs on Shared Memory Systems., ISPDC 2007: 45-52
Juan Hamers, Lieven Eeckhout, Resource prediction for media stream decoding., DATE 2007: 594-599
Juan Hamers, Lieven Eeckhout, Koen De Bosschere, Exploiting Video Stream Similarity for Energy-Efficient Decoding., MMM (2) 2007: 11-22
Juan M. Cebrian, Juan L. Aragón, José M. García, Leakage Energy Reduction in Value Predictors through Static Decay., IPDPS 2007: 1-7
Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras, Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors., Conf. Computing Frontiers 2007: 113-122
Juan Piernas, Toni Cortes, José M. García, The Design of New Journaling File Systems: The DualFS Case., IEEE Trans. Computers 56(2): 267-281 (2007)
Juan Segarra, Vicent Cholvi, Convergence of periodic broadcasting and video-on-demand., Computer Communications 30(5): 1136-1141 (2007)
Juan Touriño, Basilio B. Fraguela, Ramon Doallo, Manuel Arenaz, Special Issue: Current Trends in Compilers for Parallel Computers., Concurrency and Computation: Practice and Experience 19(18): 2313-2316 (2007)
Jukka Suhonen, Mikko Kohvakka, Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen, Cost-aware capacity optimization in dynamic multi-hop WSNs., DATE 2007: 666-671
Jun Qin, Marek Wieczorek, Kassia Plankensteiner, Thomas Fahringer, Towards a Light-weight Workflow Engine in the Asklon Grid Environment., CoreGRID 2007: 239-251
Jun Qin, Thomas Fahringer, Advanced data flow support for scientific grid workflow applications., SC 2007: 42
Kalle Holma, Mikko Setälä, Erno Salminen, Timo D. Hämäläinen, Evaluating the Model Accuracy in Automated Design Space Exploration., DSD 2007: 173-180
Karel Bruneel, Peter Bertels, Dirk Stroobandt, A Method for Fast Hardware Specialization at run-time., FPL 2007: 35-40
Karim Ammous, Nasser Benameur, Smail Niar, Java virtual machines behavior on embedded systems, SE'07: Proceedings of the 25th conference on IASTED International Multi-Conference: Software Engineering, ACTA Press, February 2007
Karthik Baddam, Mark Zwolinski, Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure., VLSI Design 2007: 854-862
Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek, Transaction-Based Communication-Centric Debug., NOCS 2007: 95-106
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic, MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture., ARC 2007: 26-38
Kenneth Hoste, Lieven Eeckhout, Microarchitecture-Independent Workload Characterization., IEEE Micro 27(3): 63-72 (2007)
Kenneth Hoste, Lieven Eeckhout, Hendrik Blockeel, Analyzing commercial processor performance numbers for predicting performance of applications of interest., SIGMETRICS 2007: 375-376
Keqiu Li, Chris R. Jesshope, Hai Jin, Jean-Luc Gaudiot, Network and Parallel Computing IFIP International Conference NPC 2007 Dalian China September 18-21 2007 Proceedings, Springer 2007
Kevin Casey, M. Anton Ertl, David Gregg, Optimizing indirect branch prediction accuracy in virtual machine interpreters., ACM Trans. Program. Lang. Syst. 29(6): (2007)
Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Increasing data-bandwidth to instruction-set extensions through register clustering., ICCAD 2007: 166-171
Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis, HARTES Toolchain Early Evaluation: Profiling Compilation and HDL Generation., FPL 2007: 402-408
Koen Bertels, Walid A. Najjar, Arjan J. van Genderen, Stamatis Vassiliadis, FPL 2007 International Conference on Field Programmable Logic and Applications Amsterdam The Netherlands 27-29 August 2007, IEEE 2007
Koen De Bosschere, David R. Kaeli, Per Stenström, David B. Whalley, Theo Ungerer, High Performance Embedded Architectures and Compilers Second International Conference HiPEAC 2007 Ghent Belgium January 28-30 2007 Proceedings, Springer 2007
Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier, High-Performance Embedded Architecture and Compilation Roadmap., T. HiPEAC 1: 5-29 (2007)
Kolin Paul, Joel Porquet, Josep Llosa, Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration., DSD 2007: 317-324
Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis, Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications., Integration 40(2): 74-93 (2007)
Kostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso, HelperCore_DB: Exploiting Multicore Technology for Databases., PACT 2007: 420
Kostas Siozios, Dimitrios Soudris, A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs., ISVLSI 2007: 55-60
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris, Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support., FPL 2007: 652-655
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris, A software-supported methodology for designing high-performance 3D FPGA architectures., VLSI-SoC 2007: 54-59
Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis, Designing Heterogeneous FPGAs with Multiple SBs., ARC 2007: 91-96
Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, Object-Relative Addressing: Compressed Pointers in 64-Bit Java Virtual Machines., ECOOP 2007: 79-100
Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, Java object header elimination for reduced memory consumption in 64-bit virtual machines., TACO 4(3): (2007)
Kristof Denolf, Adrian Chirila-Rus, Paul Schumacher, Robert Turney, Kees Vissers, Diederik Verkest, Henk Corporaal, A systematic approach to design low-power video codec cores, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Krisztián Flautner, Blurring the Layers of Abstractions: Time to Take a Step Back?, IOLTS 2007: 127
Krisztián Flautner, Architectural Trade-Offs for Fault Tolerant Multi-Core Systems., IOLTS 2007: 261
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar, Optimizing instruction-set extensible processors under data bandwidth constraints., DATE 2007: 588-593
Kyoko Iwasawa, Alan Mycroft, Choosing Method of the Most Effective Nested Loop Shearing for Parallelism., PDCAT 2007: 267-276
Kyriakos Neocleous, Marios D. Dikaiakos, Paraskevi Fragopoulou, Evangelos P. Markatos, Failure Management in Grids: the Case of the EGEE Infrastructure., Parallel Processing Letters 17(4): 391-410 (2007)
Kyriakos Stavrou, Pedro Trancoso, Thermal-aware scheduling for future chip multiprocessors, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Kyriakos Vlachos, Theofanis Orphanoudakis, Yannis Papaefstathiou, Nikos A. Nikolaou, Dionisios N. Pnevmatikatos, George E. Konstantoulakis, Jorge-A. Sanchez-P., Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units., Microprocessors and Microsystems 31(3): 188-199 (2007)
Lars Bauer, Muhammad Shafique, Dirk Teufel, Jorg Henkel, A Self-Adaptive Extensible Embedded Processor, SASO '07: Proceedings of the First International Conference on Self-Adaptive and Self-Organizing Systems, IEEE Computer Society, July 2007
Lars Bauer, Muhammad Shafique, Simon Kramer, Jörg Henkel, RISPP: rotating instruction set processing platform, DAC '07: Proceedings of the 44th annual conference on Design automation, ACM, June 2007
Laurence T. Yang, Jose G. Delgado-Frias, Yiming Li, Mohammed Niamat, Dimitrios Soudris, Srinivasa R. Vemuru, Preface of Special Issue on VLSI Design and Test, Microelectronic Engineering , Volume 84 Issue 2, Elsevier Science Ltd., February 2007
Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru, Preface., Integration 40(2): 61 (2007)
Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, N. Voros, Data Structure Exploration of Dynamic Applications., PACT 2007: 421
Lazaros Papadopoulos, Christos Baloukas, Nikolaos Zompakis, Dimitrios Soudris, Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems., ICSAMOS 2007: 58-65
Lazaros Papadopoulos, Dimitrios Soudris, System-Level Application-Specific NoC Design for Network and Multimedia Applications., PATMOS 2007: 1-9
Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Application - specific NoC platform design based on System Level Optimization., ISVLSI 2007: 311-316
Leandro Fiorin, Cristina Silvano, Mariagiovanna Sami, Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations., DSD 2007: 539-542
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano, A data protection unit for NoC-based architectures., CODES+ISSS 2007: 167-172
Lei Gao, Chao Li, Chengjun Zhu, Zhang Xiong, A Motion Compensated De-interlacing Algorithm for Motive Object Capture., HCI (12) 2007: 74-81
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, A fast and generic hybrid simulation approach using C virtual machine., CASES 2007: 3-12
Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen, Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring., SAMOS 2007: 385-395
Lennart Yseboodt, Michael De Nil, Mladen Berekovic, Electrocardiogram on Wireless Sensor Nodes., Power-aware Computing Systems 2007
Leonel Sousa, Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli., IEEE Symposium on Computer Arithmetic 2007: 240-250
Leonel Sousa, Moisés Simões Piedade, J. Germano, Teresa Mendes de Almeida, Paulo Alexandre Crisóstomo Lopes, Filipe Cardoso, Paulo Freitas, Generic Architecture Designed for Biomedical Embedded Systems., IESS 2007: 353-362
Leticia Pascual, Alejandro Torrentí, Julio Sahuquillo, Jose Flich, Understanding cache hierarchy interactions with a program-driven simulator., WCAE 2007: 30-35
Li Zhang, Chris R. Jesshope, On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores., Euro-Par Workshops 2007: 38-48
Liliana Cucu, Joël Goossens, Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systems., DATE 2007: 1635-1640
Lily R. Liang, Vinay Mandal, Yi Lu, Deepak Kumar, Multi-dimensional Cluster Misclassification Test for Pathway Differential Analysis of Diabetes., IMSCCS 2007: 84-91
Limor Fix, Orna Grumberg, Amnon Heyman, Tamir Heyman, Assaf Schuster, Verifying Very Large Industrial Circuits Using 100 Processes and Beyond., Int. J. Found. Comput. Sci. 18(1): 45-62 (2007)
Lingxiang Xiang, Jiangwei Huang, Weihua Sheng, Tianzhou Chen, The Design and Implementation of the DVS Based Dynamic Compiler for Power Reduction., APPT 2007: 233-240
Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, R. Ramanarayanan, Balaji Vaidyanathan, Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors., VLSI Design 2007: 251-258
Liping Xue, Ozcan Ozturk, Mahmut T. Kandemir, A Memory-Conscious Code Parallelization Scheme., DAC 2007: 230-233
Liza Fireman, Erez Petrank, Ayal Zaks, New Algorithms for SIMD Alignment., CC 2007: 1-15
Lotfi Mhamdi, Georgi Gaydadjiev, Stamatis Vassiliadis, Efficient Multicast Support in High-Speed Packet Switches., JNW 2(3): 28-35 (2007)
Louis-Noël Pouchet, Cédric Bastoul, Albert Cohen, Nicolas Vasilache, Iterative Optimization in the Polyhedral Model: Part I One-Dimensional Time., CGO 2007: 144-156
Luca Benini, Carlotta Guiducci, Christian Paulus, Electronic Detection of DNA Hybridization: Toward CMOS Microarrays., IEEE Design & Test of Computers 24(1): 38-48 (2007)
Luca Benini, Naehyuck Chang, Ulrich Kremer, Christian W. Probst, Power-aware Computing Systems 21.01. - 26.01.2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI) Schloss Dagstuhl Germany 2007
Luca Benini, Naehyuck Chang, Ulrich Kremer, Christian W. Probst, 07041 Abstracts Collection - Power-aware Computing Systems., Power-aware Computing Systems 2007
Luca Benini, Naehyuck Chang, Ulrich Kremer, Christian W. Probst, 07041 Summary - Power-aware Computing Systems., Power-aware Computing Systems 2007
Luca Fossati, Handshake Games., Electr. Notes Theor. Comput. Sci. 171(3): 21-41 (2007)
Luca Fossati, Pier Luca Lanzi, Kumara Sastry, David E. Goldberg, Osvaldo Gómez, A Simple Real-Coded Extended Compact Genetic Algorithm., IEEE Congress on Evolutionary Computation 2007: 342-348
Ludo Van Put, Dominique Chanet, Koen De Bosschere, Whole-program linear-constant analysis with applications to link-time optimization., SCOPES 2007: 61-70
Luis A. Plana, Steve B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang, A GALS Infrastructure for a Massively Parallel Multiprocessor, IEEE Design & Test , Volume 24 Issue 5, IEEE Computer Society Press, September 2007
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Victor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity., SIGARCH Computer Architecture News 35(4): 37-44 (2007)
Luis Orozco-Barbosa, Pedro Cuenca, Editorial., Telecommunication Systems 36(1-3): 1-2 (2007)
Lurng-Kuo Liu, Qiang Liu, Apostol Natsev, Kenneth A. Ross, John R. Smith, Ana Lucia Varbanescu, Digital Media Indexing on the Cell Processor., ICME 2007: 1866-1869
M. Goyeneche, Jesús E. Villadangos, José Javier Astrain, Manuel Prieto, Alberto Córdoba, A Distributed Data Gathering Algorithm for Wireless Sensor Networks with Uniform Architecture., PDP 2007: 373-380
M. Hartmann, V. Pantazis, Tom Vander Aa, Mladen Berekovic, Christian Hochberger, Bjorn De Sutter, Still Image Processing on Coarse-Grained Reconfigurable Array Architectures., ESTImedia 2007: 67-72
M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli, Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays., ICCAD 2007: 765-772
M. M. Waliullah, Per Stenström, Starvation-Free Transactional Memory-System Protocols., Euro-Par 2007: 280-291
M. M. Waliullah, Per Stenstrom, Starvation-free commit arbitration policies for transactional memory systems, SIGARCH Computer Architecture News , Volume 35 Issue 1, ACM, March 2007
Magnus Själander, Per Larsson-Edefors, Magnus Björk, A Flexible Datapath Interconnect for Embedded Applications., ISVLSI 2007: 15-20
Mahmood Ahmadi, Stephan Wong, Modified collision packet classification using counting bloom filter in tuple space., Parallel and Distributed Computing and Networks 2007: 295-300
Mahmood Ahmadi, Stephan Wong, A performance model for network processor architectures in packet processing system, PDCS '07: Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems, ACTA Press, November 2007
Mahmood Ahmadi, Stephan Wong, A Cache Architecture for Counting Bloom Filters., ICON 2007: 218-223
Mahmut T. Kandemir, Ozcan Ozturk, Vijay Degalahal, Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings., VLSI Design 2007: 227-232
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son, Ozcan Ozturk, Memory bank aware dynamic loop scheduling., DATE 2007: 1671-1676
Malgorzata Steinder, Ian Whalley, David Carrera, Ilona Gaweda, David M. Chess, Server virtualization in autonomic management of heterogeneous workloads., Integrated Network Management 2007: 139-148
Manish Verma, Peter Marwedel, Advanced Memory Optimization Techniques for Low-Power Embedded Processors, 1st edition, Advanced Memory Optimization Techniques for Low-Power Embedded Processors, 1st edition, Springer Publishing Company, Incorporated, May 2007
Manoj Gupta, Fermín Sánchez, Josep Llosa, Merge Logic for Clustered Multithreaded VLIW Processors., DSD 2007: 353-360
Manoj Gupta, Fermín Sánchez, Josep Llosa, Cluster-level simultaneous multithreading for VLIW processors., ICCD 2007: 121-128
Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksrishnan, Energy Based Design Space Exploration of Multiprocessor VLIW Architectures., DSD 2007: 307-310
Manolis Marazakis, Vassilis Papaefstathiou, Angelos Bilas, Optimization and bottleneck analysis of network block I/O in commodity storage systems., ICS 2007: 33-42
Manuel Arenaz, Juan Touriño, Ramon Doallo, Program Behavior Characterization Through Advanced Kernel Recognition., Euro-Par 2007: 237-247
Manuel Nickschas, Uwe Brinkschulte, Using Multi-Agent Principles for Implementing an Organic Real-Time Middleware., ISORC 2007: 189-195
María Dolores R-Moreno, Manuel Prieto, Daniel Meziat, AN AI ELECTRICAL GROUND SUPPORT EQUIPMENT FOR CONTROLLING AND TESTING A SPACE INSTRUMENT, Applied Artificial Intelligence , Volume 21 Issue 2, Taylor & Francis, Inc., February 2007
María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida, Area optimization of multi-cycle operators in high-level synthesis., DATE 2007: 449-454
María Dolores Rodríguez-Moreno, Manuel Prieto, Daniel Meziat, An AI Electrical Ground Support Equipment for Controlling and Testing a Space Instrument., Applied Artificial Intelligence 21(2): 81-98 (2007)
Marc Casas, Rosa M. Badia, Jesús Labarta, Automatic Structure Extraction from MPI Applications Tracefiles., Euro-Par 2007: 3-12
Marc Casas, Rosa M. Badia, Jesús Labarta, Automatic Phase Detection of MPI Applications., PARCO 2007: 129-136
Marc Daumas, David Lester, Stochastic Formal Methods: An Application to Accuracy of Numeric Software., HICSS 2007: 262
Marc Duranton, Programmable Engines for Embedded Systems: The New Challenges., ISQED 2007: 556-557
Marc Sanchez Artigas, Pedro Garcia Lopez, Antonio F. Skarmeta, A Comparative Study of Hierarchical DHT Systems, LCN '07: Proceedings of the 32nd IEEE Conference on Local Computer Networks, IEEE Computer Society, October 2007
Marcel Arrufat, Gerard Paris, Pedro Garcia Lopez, Antonio F. Gomez Skarmeta, SCOMET: Adapting Collaborative Working Environments to the MANET Scenario, WETICE '07: Proceedings of the 16th IEEE International Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprises, IEEE Computer Society, June 2007
Marcello Mura, Marco Paolieri, SC2 StateCharts to SystemC: Automatic Executable Models Generation., FDL 2007: 198-203
Marcello Mura, Marco Paolieri, Luca Negri, Mariagiovanna Sami, StateCharts to systemc: a high level hardware simulation approach., ACM Great Lakes Symposium on VLSI 2007: 505-508
Marco Aldinucci, Marco Danelutto, The cost of security in skeletal systems., PDP 2007: 213-220
Marco Aldinucci, Marco Danelutto, Skeleton-based parallel programming: Functional and parallel semantics in a single shot., Computer Languages Systems & Structures 33(3-4): 179-192 (2007)
Marco Aldinucci, Marco Danelutto, Massimo Torquati, Francesco Polzella, Gianmarco Spinatelli, Marco Vanneschi, Alessandro Gervaso, Manuel Cacitti, Pierfrancesco Zuccato, VirtuaLinux: Virtualized High-Density Clusters with no Single Point of Failure., PARCO 2007: 355-362
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, Adding metadata to Orc to support reasoning about grid programs., CoreGRID 2007: 205-214
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, Management in Distributed Systems: A Semi-formal Approach., Euro-Par 2007: 651-661
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, A Framework for Prototyping and Reasoning about Distributed Systems., PARCO 2007: 235-242
Marco Alexandre Cravo Gomes, Gabriel Falcão Paiva Fernandes, Vítor Manuel Mendes da Silva, Vitor Ferreira, Alexandre Sengo, Miguel Falcão, Flexible Parallel Architecture for DVB-S2 LDPC Decoders., GLOBECOM 2007: 3265-3269
Marco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto, A novel SoC design methodology combining adaptive software and reconfigurable hardware., ICCAD 2007: 303-308
Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero, Implicit Transactional Memory in Kilo-Instruction Multiprocessors., Asia-Pacific Computer Systems Architecture Conference 2007: 339-353
Marco Mantovani, Simone Leardini, Martino Ruggiero, Andrea Acquaviva, Luca Benini, A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip., ACM Great Lakes Symposium on VLSI 2007: 509-512
Marco Paolieri, Ivano Bonesana, Marco D. Santambrogio, ReCPU: A parallel and pipelined architecture for regular expression matching., VLSI-SoC 2007: 19-24
Maria Andréia Formico Rodrigues, Ricardo Régis Cavalcante Chaves, Performance and user based analysis of a collaborative virtual environment system, GRAPHITE '07: Proceedings of the 5th international conference on Computer graphics and interactive techniques in Australia and Southeast Asia, ACM, December 2007
Marina Alonso, Salvador Coll, Vicente Santonja, Juan Miguel Martínez, Pedro López, José Duato, Power-Aware Fat-Tree Networks Using On/Off Links., HPCC 2007: 472-483
Marina Biberstein, Eitan Farchi, Shmuel Ur, Choosing among alternative pasts., Concurrency and Computation: Practice and Experience 19(3): 341-353 (2007)
Mark Thompson, Andy D. Pimentel, Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration., SAMOS 2007: 222-232
Mark Thompson, Hristo Nikolov, Todor Stefanov, Andy D. Pimentel, Cagkan Erbas, Simon Polstra, Ed F. Deprettere, A framework for rapid system-level exploration synthesis and programming of multimedia MP-SoCs., CODES+ISSS 2007: 9-14
Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner, The Next Generation Challenge for Software Defined Radio., SAMOS 2007: 343-354
Martin Karlsson, Erik Hagersten, Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution., IPDPS 2007: 1-10
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, SAT-decoding in evolutionary algorithms for discrete constrained optimization problems., IEEE Congress on Evolutionary Computation 2007: 935-942
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Solving Multi-objective Pseudo-Boolean Problems., SAT 2007: 56-69
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström, FlexCore: Utilizing Exposed Datapath Control for Efficient Computing., ICSAMOS 2007: 18-25
Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci, A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes., GLOBECOM 2007: 3270-3274
Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci, A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes., VLSI-SoC 2007: 236-241
Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda, The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer., VLSI Signal Processing 47(1): 15-31 (2007)
Matteo Giaconia, Marco Macchetti, Francesco Regazzoni, Kai Schramm, Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes., VLSI Design 2007: 731-737
Matteo Giani, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto, Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity., ERSA 2007: 78-84
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, Exploration of distributed shared memory architectures for NoC-based multiprocessors., Journal of Systems Architecture 53(10): 719-732 (2007)
Matthew Barnes, Hugh Leather, D. K. Arvind, Emergency Evacuation using Wireless Sensor Networks., LCN 2007: 851-857
Matthew Curtis-Maury, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, A comparison of online and offline strategies for program adaptation., ACM Southeast Regional Conference 2007: 162-167
Matthew Curtis-Maury, Karan Singh, Sally A. McKee, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz, Identifying energy-efficient concurrency levels using machine learning., CLUSTER 2007: 488-495
Matthias Alles, Torben Brack, Norbert Wehn, A Reliability-Aware LDPC Code Decoding Algorithm., VTC Spring 2007: 1544-1548
Matthias May, Christian Neeb, Norbert Wehn, Evaluation of High Throughput Turbo-Decoder Architectures., ISCAS 2007: 2770-2773
Matthias Woehrle, Christian Plessl, Jan Beutel, Lothar Thiele, Increasing the reliability of wireless sensor networks with a distributed testing framework., EmNets 2007: 93-97
Matthieu Leclercq, Ali Erdem Özcan, Vivien Quéma, Jean-Bernard Stefani, Supporting Heterogeneous Architecture Descriptions in an Extensible Toolset., ICSE 2007: 209-219
Mauri Kuorilehto, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen, Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network., SAMOS 2007: 396-407
Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen, SensorOS: A New Operating System for Time Critical WSN Applications., SAMOS 2007: 431-442
Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero, Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications., ISPASS 2007: 62-71
Mauricio Alvarez, Esther Salami, Alex Ramirez, Mateo Valero, HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications, IISWC '07: Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization - Volume 00 , Volume 00, IEEE Computer Society, September 2007
Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania, Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms., IPDPS 2007: 1-8
Md. Mafijul Islam, On the Limitations of Compilers to Exploit Thread-Level Parallelism in Embedded Applications., ACIS-ICIS 2007: 60-66
Md. Mafijul Islam, Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications., SBAC-PAD 2007: 54-61
Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström, Loop-level Speculative Parallelism in Embedded Applications., ICPP 2007: 3
Md. Mafijul Islam, Per Stenström, Energy and Performance Trade-offs between Instruction Reuse and Trivial Computations for Embedded Applications., SIES 2007: 86-93
Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar, Adaptive Sampling for Efficient MPSoC Architecture Simulation., MASCOTS 2007: 186-192
Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang, A Combined Hardware/Software Optimization Framework for Signal Representation and Recognition., International Conference on Computational Science (1) 2007: 1230-1237
Michael Behar, Avi Mendelson, Avinoam Kolodny, Trace cache sampling filter., ACM Trans. Comput. Syst. 25(1): (2007)
Michael Dalton, Hari Kannan, Christos Kozyrakis, Raksha: a flexible information flow architecture for software security., ISCA 2007: 482-493
Michael F. P. O'Boyle, François Bodin, José González, Lucian N. Vintan, Topic 4 High-Performance Architectures and Compilers., Euro-Par 2007: 235
Michael F. P. O'Boyle, François Bodin, Marcelo Cintra, Introduction to Part 2., T. HiPEAC 1: 139 (2007)
Michael Ferdman, Babak Falsafi, Last-Touch Correlated Data Streaming., ISPASS 2007: 105-115
Michael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich, Interactive presentation: Reliability-aware system synthesis., DATE 2007: 409-414
Michael Klemm, Jean Christophe Beyler, Ronny T. Lampert, Michael Philippsen, Philippe Clauss, Esodyp+: Prefetching in the Jackal Software DSM., Euro-Par 2007: 563-573
Michael Med, Andreas Krall, Instruction Set Encoding Optimization for Code Size Reduction., ICSAMOS 2007: 9-17
Michael Sass Hansen, Hildur Ólafsdóttir, Tron A. Darvann, Nuno V. Hermann, Estanislao Oubel, Rasmus Larsen, Bjarne K. Ersbøll, Alejandro F. Frangi, Per Larsen, Chad A. Perlyn, Gil, Estimation of Independent Non-Linear Deformation Modes for Analysis of Craniofacial Malformations in Crouzon Mice., ISBI 2007: 1296-1299
Michael Van Biesbrouck, Lieven Eeckhout, Brad Calder, Representative Multiprogram Workloads for Multithreaded Processor Simulation, IISWC '07: Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization - Volume 00 , Volume 00, IEEE Computer Society, September 2007
Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Automated framework for partitioning DSP applications in hybrid reconfigurable platforms., Microprocessors and Microsystems 31(1): 1-14 (2007)
Michalis Polychronakis, Kostas G. Anagnostakis, Evangelos P. Markatos, Emulation-Based Detection of Non-self-contained Polymorphic Shellcode., RAID 2007: 87-106
Michalis Polychronakis, Kostas G. Anagnostakis, Evangelos P. Markatos, Network-level polymorphic shellcode detection using emulation., Journal in Computer Virology 2(4): 257-274 (2007)
Miguel Lozano, Juan M. Orduña, Vicente Cavero, A Genetic Approach for Distributing Semantic Databases of Crowd Simulations., IPDPS 2007: 1-8
Miguel Lozano, Pedro Morillo, Juan M. Orduña, Vicente Cavero, On the Design of an Efficient Architecture for Supporting Large Crowds of Autonomous Agents., AINA 2007: 716-723
Miguel Peon-Quiros, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris, Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption., PATMOS 2007: 373-383
Miguel Ribeiro, Leonel Sousa, A Run-time Reconfigurable Processor for Video Motion Estimation., FPL 2007: 726-729
Miloš Milovanović, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrian Cristal, Eduard Ayguadé, Mateo Valero, Multithreaded software transactional memory and OpenMP, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Milos Milovanovic, Roger Ferrer, Osman S. Unsal, Adrián Cristal, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Transactional Memory and OpenMP., IWOMP 2007: 37-53
Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson, Overdrive Power-Gating Techniques for Total Power Minimization., ISVLSI 2007: 125-132
Minh B. Do, J. Benton, Menkes Van Den Briel, Subbarao Kambhampati, Planning with goal utility dependencies, IJCAI'07: Proceedings of the 20th international joint conference on Artifical intelligence, Morgan Kaufmann Publishers Inc., January 2007
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson, Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays., ISQED 2007: 185-191
Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis, High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process., DSD 2007: 249-256
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Online Prediction of Applications Cache Utility., ICSAMOS 2007: 169-177
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, MLP-Aware Dynamic Cache Partitioning., PACT 2007: 418
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Explaining Dynamic Cache Partitioning Speed Ups., Computer Architecture Letters 6(1): 1-4 (2007)
Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero, A Flexible Heterogeneous Multi-Core Architecture., PACT 2007: 13-24
Mirko Loghi, Luca Benini, Massimo Poncino, Power macromodeling of MPSoC message passing primitives., ACM Trans. Embedded Comput. Syst. 6(4): (2007)
Mladen Berekovic, Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring., DSD 2007: 16-18
Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel, Run-time adaptive on-chip communication scheme, ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, IEEE Press, November 2007
Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari, Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors., AICCSA 2007: 528-534
Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi, A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services., DDECS 2007: 247-250
Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi, A UML Based System Level Failure Rate Assessment Technique for SoC Designs., VTS 2007: 243-248
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi, Low test application time resource binding for behavioral synthesis., ACM Trans. Design Autom. Electr. Syst. 12(2): (2007)
Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi, A New Approach for Design and Verification of Transaction Level Models., ISCAS 2007: 3760-3763
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi, On-Chip Verification of NoCs Using Assertion Processors., DSD 2007: 535-538
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi, Functional Test-Case Generation by a Control Transaction Graph for TLM Verification., DSD 2007: 157-164
Mohammad Reza Nami, Koen Bertels, A Survey of Autonomic Computing Systems, ICAS '07: Proceedings of the Third International Conference on Autonomic and Autonomous Systems, IEEE Computer Society, June 2007
Mohammed Fellahi, Albert Cohen, Sid Touati, Code-size conscious pipelining of imperfectly nested loops, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Montserrat Bóo, Margarita Amor, Jürgen Döllner, Unified Hybrid Terrain Representation Based on Local Convexifications., GeoInformatica 11(3): 331-357 (2007)
Mostafa I. H. Abd-El-Barr, Salman A. Khan, Design and analysis of a fault tolerant hybrid mobile scheme, Information Sciences: an International Journal , Volume 177 Issue 12, Elsevier Science Inc., June 2007
Mourad Alia, Viktor S. Wold Eide, Nearchos Paspallis, Frank Eliassen, Svein O. Hallsteinsen, George A. Papadopoulos, A Utility-Based Adaptivity Model for Mobile Applications, AINAW '07: Proceedings of the 21st International Conference on Advanced Information Networking and Applications Workshops - Volume 02 , Volume 02, IEEE Computer Society, May 2007
Muhammad Omer Cheema, Lionel Lacassagne, Omar Hammami, System-platforms-based SystemC TLM design of image processing chains for embedded applications, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Muhammad Omer Cheema, Omar Hammami, Lionel Lacassagne, Alain Merigot, Hardware /software codesign of image processing applications using Transaction Level Modeling, ASAP '07: Proceedings of the 2007 IEEE International Conf. on Application-Specific Systems, Architectures and Processors (ASAP) - Volume 00 , Volume 00, IEEE Computer Society, July 2007
Mumtaz Siddiqui, Alex Villazón, Thomas Fahringer, Semantic-Based On-demand Synthesis of Grid Activities for Automatic Workflow Generation., eScience 2007: 43-50
Mumtaz Siddiqui, Thomas Fahringer, Semantically-enhanced on-demand resource provision and management for the grid., Multiagent and Grid Systems 3(3): 327-339 (2007)
N. Pete Sedcole, Peter Y. K. Cheung, Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis., FPGA 2007: 178-187
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Run-Time Integration of Reconfigurable Video Processing Systems., IEEE Trans. VLSI Syst. 15(9): 1003-1016 (2007)
Nabil Hasasneh, Ian Bell, Chris R. Jesshope, High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids., AICCSA 2007: 301-308
Nabil Hasasneh, Ian Bell, Chris R. Jesshope, Asynchronous arbiter for micro-threaded chip multiprocessors., Journal of Systems Architecture 53(5-6): 253-262 (2007)
Nadine Azémard, Lars J. Svensson, Integrated Circuit and System Design. Power and Timing Modeling Optimization and Simulation 17th International Workshop PATMOS 2007 Gothenburg Sweden September 3-5 2007 Proceedings, Springer 2007
Nathan Clark, Amir Hormati, Sami Yehia, Scott A. Mahlke, Krisztián Flautner, Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping., HPCA 2007: 216-227
Neil Bergmann, Marco Platzner, Jürgen Teich, Editorial: dynamically reconfigurable architectures, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Neil W. Bergmann, Yi Lu, John A. Williams, Automatic Self-Reconfiguration of System-on-Chip Peripherals., FCCM 2007: 313-316
Nhut Thanh Quach, Bahman Zafarifar, G. N. Gaydadjiev, Real-time FPGA-implementation for blue-sky Detection., ASAP 2007: 76-82
Nicholas Beck, Ian Johnson, Shaping TinyOS to deal with evolving device architectures: experiences porting TinyOS-2.0 to the Chipcon CC2430., EmNets 2007: 83-87
Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni, Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems., DSD 2007: 361-368
Nicolas Fournel, Antoine Fraboulet, Guillaume Chelius, Eric Fleury, Bruno Allard, Olivier Brevet, Worldsens: from lab to sensor network application development and deployment., IPSN 2007: 551-552
Nicolas Fournel, Antoine Fraboulet, Paul Feautrier, Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements., PATMOS 2007: 10-19
Nicolas Fournel, Antoine Fraboulet, Paul Feautrier, eSimu: a Fast and Accurate Energy Consumption Simulator for Real Embedded System., WOWMOM 2007: 1-6
Nicolas Guil, J. M. González-Linares, Julián Ramos Cózar, Emilio L. Zapata, A Clustering Technique for Video Copy Detection., IbPRIA (1) 2007: 451-458
Nicolas Vasilache, Albert Cohen, Louis-Noël Pouchet, Automatic Correction of Loop Transformations., PACT 2007: 292-304
Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha, Tutorial 5: SoC Communication Architectures: Technology Current Practice Research and Trends., VLSI Design 2007: 8
Nikolaos Chrysos, Congestion management for non-blocking clos networks., ANCS 2007: 117-126
Nikolaos Zompakis, Lazaros Papadopoulos, Georgios Ch. Sirakoulis, Dimitrios Soudris, Implementing cellular automata modeled applications on network-on-chip platforms., VLSI-SoC 2007: 288-291
Nikolas Kroupis, Dimitrios Soudris, Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate., PATMOS 2007: 505-515
Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson, Naju Mancheril, Anastassia Ailamaki, Babak Falsafi, Database Servers on Chip Multiprocessors: Limitations and Opportunities., CIDR 2007: 79-87
Nikos Pogkas, George E. Karastergios, Christos D. Antonopoulos, Stavros A. Koubias, George Papadopoulos, Architecture Design and Implementation of an Ad-Hoc Network for Disaster Relief Operations., IEEE Trans. Industrial Informatics 3(1): 63-72 (2007)
Nils Agne Nordbotten, Tor Skeie, A Routing Methodology for Dynamic Fault Tolerance in Meshes and Tori., HiPC 2007: 514-527
Nitzan Peleg, Bilha Mendelson, Detecting Change in Program Behavior for Adaptive Optimization., PACT 2007: 150-162
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun, ATLAS: a chip-multiprocessor with transactional memory support., DATE 2007: 3-8
Nuno Roma, Leonel Sousa, Efficient hybrid DCT-domain algorithm for video spatial downscaling, EURASIP Journal on Advances in Signal Processing , Volume 2007 Issue 2, Hindawi Publishing Corp., June 2007
Ohad Shacham, Mooly Sagiv, Assaf Schuster, Scaling model checking of dataraces using dynamic information., J. Parallel Distrib. Comput. 67(5): 536-550 (2007)
Oliver Schliebusch, Heinrich Meyr, Rainer Leupers, Optimized ASIP Synthesis from Architecture Description Language Models, Optimized ASIP Synthesis from Architecture Description Language Models, Springer-Verlag New York, Inc., February 2007
Oliverio J. Santana, Alex Ramírez, Mateo Valero, Enlarging Instruction Streams., IEEE Trans. Computers 56(10): 1342-1357 (2007)
Olivier Zendra, Eric Jul, Roland Ducournau, Etienne Gagnon, Richard E. Jones, Chandra Krintz, Philippe Mulet, Jan Vitek, Implementation Compilation Optimization of Object-Oriented Languages Programs and Systems., ECOOP Workshops 2007: 50-64
Orna Grumberg, Assaf Schuster, Avi Yadgar, 3-Valued Circuit SAT for STE with Automatic Refinement., ATVA 2007: 457-473
Ozcan Ozturk, Guilin Chen, Mahmut T. Kandemir, Mustafa Karaköy, Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems., CGO 2007: 232-243
Ozcan Ozturk, Mahmut T. Kandemir, Seung Woo Son, An ilp based approach to reducing energy consumption in nocbased CMPS., ISLPED 2007: 411-414
Pål Grønsund, Paal Engelstad, Moti Ayoun, Tor Skeie, Real Life Field Trial over a Pre-mobile WiMAX System with 4th Order Diversity., NEW2AN 2007: 121-132
Pål Grønsund, Paal Engelstad, Torbjørn Johnsen, Tor Skeie, The physical performance and path loss in a fixed WiMAX deployment., IWCMC 2007: 439-444
Pablo Abad, Valentin Puente, José-Ángel Gregorio, Pablo Prieto, Rotary router: an efficient architecture for CMP interconnection networks., ISCA 2007: 116-125
Panagiota Fatourou, Nikolaos D. Kallimanis, Time-optimal space-efficient single-scanner snapshots & multi-scanner snapshots using CAS., PODC 2007: 33-42
Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen, Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks., SAMOS 2007: 443-453
Paola Caymes-Scutari, Anna Morajko, Tomàs Margalef, Emilio Luque, Automatic Generation of Dynamic Tuning Techniques., Euro-Par 2007: 13-22
Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro, A Digit-by-Digit Algorithm for mth Root Extraction., IEEE Trans. Computers 56(12): 1696-1706 (2007)
Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne, Introduction of Architecturally Visible Storage in Instruction Set Extensions., IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 435-446 (2007)
Paul Carpenter, David Ródenas, Xavier Martorell, Alex Ramírez, Eduard Ayguadé, A Streaming Machine Description and Programming Model., SAMOS 2007: 107-116
Paul Kaufmann, Marco Platzner, MOVES: A Modular Framework for Hardware Evolution., AHS 2007: 447-454
Paul Kaufmann, Marco Platzner, Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution., ARCS 2007: 199-208
Paul Lokuciejewski, Heiko Falk, Martin Schwarzer, Peter Marwedel, Henrik Theiling, Influence of procedure cloning on WCET prediction., CODES+ISSS 2007: 137-142
Paula Cecilia Fritzsche, Dolores Rexachs, Emilio Luque, A Computational Approach to TSP Performance Prediction Using Data Mining., AINA Workshops (1) 2007: 252-259
Paula Cecilia Fritzsche, Dolores Rexachs, Emilio Luque, A knowledge-based methodology to predict performance order of data-dependent applications., DMIN 2007: 359-368
Paula Cecilia Fritzsche, Dolores Rexachs, Emilio Luque, Extracting Knowledge to Predict TSP Asymptotic Time Complexity., ICDM Workshops 2007: 309-318
Paula Cecilia Fritzsche, Dolores Rexachs, Emilio Luque, Applying Data Mining to Define TSP Asymptotic Time Complexity., ICTAI (2) 2007: 189-192
Paulo Alexandre Crisóstomo Lopes, J. Germano, T. M. Almeida, Leonel Sousa, Moisés Simões Piedade, Filipe Cardoso, H. A. Ferreira, P. P. Freitas, A New Handheld Biochip-based Microsystem., ISCAS 2007: 2379-2382
Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso, Reconfigurable Computing: Architectures Tools and Applications Third International Workshop ARC 2007 Mangaratiba Brazil March 27-29 2007., Springer 2007
Pedro Garcia Lopez, Marc Sanchez Artigas, Jordi Pujol Ahull, The p2pWeb Model: A Glue for the Web, WETICE '07: Proceedings of the 16th IEEE International Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprises, IEEE Computer Society, June 2007
Pedro Morillo, Silvia Rueda, Juan M. Orduña, José Duato, A Latency-Aware Partitioning Method for Distributed Virtual Environment Systems., IEEE Trans. Parallel Distrib. Syst. 18(9): 1215-1226 (2007)
Pedro Trancoso, Watt Matters Most? Design Space Exploration of High-Performance Microprocessors for Power-Performance Efficiency., Journal of Circuits Systems and Computers 16(3): 357-378 (2007)
Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala, Resource Conflict Detection in Simulation of Function Unit Pipelines., SAMOS 2007: 233-240
Pepijn J. de Langen, Ben H. H. Juurlink, Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors., SAMOS 2007: 75-85
Per Stenström, IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises?, IPDPS 2007: 14
Per Stenström, Introduction to Part 1., T. HiPEAC 1: 33 (2007)
Per Stenström, Michael F. P. O'Boyle, François Bodin, Marcelo Cintra, Sally A. McKee, Transactions on High-Performance Embedded Architectures and Compilers I, Springer 2007
Peter Benner, Maribel Castillo, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Stabilizing large-scale generalized systems on parallel computers using multithreading and message-passing., Concurrency and Computation: Practice and Experience 19(4): 531-542 (2007)
Peter van Stralen, Andy D. Pimentel, Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration., ESTImedia 2007: 33-38
Petri Kukkala, Mikko Setälä, Tero Arpinen, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Implementing a WLAN video terminal using UML and fully automated design flow, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Philip Brisk, Ajay K. Verma, Paolo Ienne, An optimistic and conservative register assignment heuristic for chordal graphs., CASES 2007: 209-217
Philip Brisk, Ajay K. Verma, Paolo Ienne, Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design., ICCAD 2007: 172-179
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar, Enhancing FPGA Performance for Arithmetic Circuits., DAC 2007: 334-337
Philippe Faes, Mark Christiaens, Dirk Stroobandt, Mobility of Data in Distributed Hybrid Computing Systems., IPDPS 2007: 1-7
Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser, Massively parallel processing on a chip., Conf. Computing Frontiers 2007: 277-286
Philippe Millet, Jean-Claude Heudin, Web Mining in the EVA Intelligent Agent Architecture., Web Intelligence/IAT Workshops 2007: 368-371
Pierfrancesco Foglia, F. Giuntoli, Cosimo Antonio Prete, Michele Zanda, Assisting e-government users with animated talking faces., Interactions 14(1): 24-26 (2007)
Piero Zappi, Elisabetta Farella, Luca Benini, Enhancing the spatial resolution of presence detection in a PIR based wireless surveillance network., AVSS 2007: 295-300
Pierre Boulet, Philippe Marquet, Éric Piel, Julien Taillard, Repetitive Allocation Modelling with MARTE., FDL 2007: 280-285
Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou, A study of thread migration in temperature-constrained multicores., TACO 4(2): (2007)
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal, Very wide register: an asymmetric register file organization for low power embedded processors., DATE 2007: 1066-1071
Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo, Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors., ISCAS 2007: 121-124
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung, Automatic On-chip Memory Minimization for Data Reuse, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Quan Shi, Ning Xi, Weihua Sheng, Recursive Measurement Process for Improving Accuracy of Dimensional Inspection of Automotive Body Parts., ICRA 2007: 4764-4769
R. González-del-Campo, F. Sáenz-Pérez, Programmed Search in a Timetabling Problem over Finite Domains, Electronic Notes in Theoretical Computer Science (ENTCS) , Volume 177, Elsevier Science Publishers B. V., June 2007
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Comparing the latency performance of the DTable and DRR schedulers., IPDPS 2007: 1-8
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser, An MPSoC Performance Estimation Framework Using Transaction Level Modeling., RTCSA 2007: 525-533
Radu Prodan, Thomas Fahringer, Grid Computing Experiment Management Tool Integration and Scientific Workflows, Springer 2007
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Houcine Hassan, Pedro Lopez, Leakage Current Reduction in Data Caches on Embedded Systems, IPC '07: Proceedings of the The 2007 International Conference on Intelligent Pervasive Computing, IEEE Computer Society, October 2007
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors., SBAC-PAD 2007: 62-68
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato, VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors., PACT 2007: 429
Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou, Synthetic Trace-Driven Simulation of Cache Memory., AINA Workshops (1) 2007: 764-771
Raimund Kirner, Jens Knoop, Adrian Prantl, Markus Schordan, Ingomar Wenzel, WCET Analysis: The Annotation Language Challenge., WCET 2007
Rami Rom, Jacob Erel, Michael Glikson, Randy A. Lieberman, Kobi Rosenblum, Ofer Binah, Ran Ginosar, David L. Hayes, Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme., IEEE Transactions on Neural Networks 18(2): 542-550 (2007)
Ramon Nou, Ferran Julià, David Carrera, Kevin Hogan, Jordi Caubet, Jesús Labarta, Jordi Torres, Monitoring and Analysis Framework for Grid Middleware., PDP 2007: 129-133
Raul Wirz, Raúl Marín, José M. Claver, Josep Fernández, Enric Cervera, Transport Protocols for Remote Programming of Network Robots within the context of Telelaboratories for Education: A Comparative Analysis., ICCCN 2007: 1315-1320
Ravi K. Garimella, Weihua Sheng, Dynamic localization of multiple mobile subjects in wireless Ad Hoc networks., IROS 2007: 2003-2008
Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor, Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method., IEEE Trans. VLSI Syst. 15(8): 952-962 (2007)
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato, A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures., HPCA 2007: 157-168
Ricardo Fernandez-Pascual, Jose M. Garcia, Manuel E. Acacio, Jose Duato, A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures, HPCA '07: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, IEEE Computer Society, February 2007
Ricardo Ferreira, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso, A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures., ISVLSI 2007: 61-66
Ricardo Menotti, Eduardo Marques, João M. P. Cardoso, Aggressive Loop Pipelining for Reconfigurable Architectures., FPL 2007: 501-502
Richard Tran Mills, Chuan Yue, Andreas Stathopoulos, Dimitrios S. Nikolopoulos, Runtime and Programming Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory., J. Grid Comput. 5(2): 213-234 (2007)
Richard Vincent Bennett, Alastair Colin Murray, Björn Franke, Nigel P. Topham, Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems., LCTES 2007: 83-92
Rickard Holsmark, Shashi Kumar, Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks., J. Inf. Sci. Eng. 23(6): 1649-1662 (2007)
Rob Hoes, Twan Basten, Chen-Khong Tham, Marc Geilen, Henk Corporaal, Analysing qos trade-offs in wireless sensor networks., MSWiM 2007: 60-69
Robbie Schaefer, Wolfgang Mueller, Andres Marán López, Daniel Díaz Sánchez, Using smart cards for secure and device independent user interfaces, Mobility '07: Proceedings of the 4th international conference on mobile technology, applications, and systems and the 1st international symposium on Computer human interaction in mobile technology, ACM, September 2007
Robert Pyka, Christoph Faßbach, Manish Verma, Heiko Falk, Peter Marwedel, Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications., SCOPES 2007: 41-50
Roberto Giorgi, Paolo Bennati, Reducing leakage in power-saving capable caches for embedded systems by using a filter cache, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems., SBAC-PAD 2007: 263-270
Roberto R. Osorio, Javiefr D. Bruguera, Entropy Coding on a Programmable Processor Array for Multimedia SoC, IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP)
Roberto R. Osorio, Javier D. Bruguera, Entropy Coding on a Programmable Processor Array for Multimedia SoC., ASAP 2007: 222-227
Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis, A Quantitative Prediction Model for Hardware/Software Partitioning., FPL 2007: 735-739
Ron Gabor, Shlomo Weiss, Avi Mendelson, Fairness enforcement in switch on event multithreading., TACO 4(3): (2007)
Rong Huang, Shurong Tong, Weihua Sheng, Zhun Fan, A Problem Solving Environment for Combinatorial Optimization Based on Parallel Meta-heuristics., CIRA 2007: 432-437
Rosa Filgueira, David E. Singh, Florin Isaila, Jesús Carretero, Antonio Garcia Loureiro, Optimization and evaluation of parallel I/O in BIPS3D parallel irregular application., IPDPS 2007: 1-8
Rosa M. Badia, Christian Pérez, Artur Andrzejak, Alvaro Arenas, Topic 6 Grid and Cluster Computing., Euro-Par 2007: 359
Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon, QNoC Asynchronous Router with Dynamic Virtual Channel Allocation., NOCS 2007: 218
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny, High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link., ASYNC 2007: 3-14
Rubing Duan, Radu Prodan, Thomas Fahringer, Performance and cost optimization for multiple large-scale grid workflow applications., SC 2007: 12
Rui Rodrigues, João M. P. Cardoso, On Pipelining Sequences of Data-Dependent Loops., J. UCS 13(3): 419-439 (2007)
Rui Rodrigues, Joao M. P. Cardoso, Pedro C. Diniz, A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli, Timing-Error-Tolerant Network-on-Chip Design Methodology., IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1297-1310 (2007)
Ryan Johnson, Nikos Hardavellas, Ippokratis Pandis, Naju Mancheril, Stavros Harizopoulos, Kivanc Sabirli, Anastassia Ailamaki, Babak Falsafi, To Share or Not To Share?, VLDB 2007: 351-362
Ryan Johnson, Stavros Harizopoulos, Nikos Hardavellas, Kivanc Sabirli, Ippokratis Pandis, Anastasia Ailamaki, Naju G. Mancheril, Babak Falsafi, To share or not to share?, VLDB '07: Proceedings of the 33rd international conference on Very large data bases, VLDB Endowment, September 2007
Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser, A Design Flow to Map Parallel Applications onto FPGAs., FPL 2007: 605-608
Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser, Multiple Abstraction Views of FPGA to Map Parallel Applications., ReCoSoC 2007: 90-97
Sérgio F. Martins, Leonel Sousa, João Martins, Additive Logistic Regression Applied to Retina Modelling., ICIP (3) 2007: 309-312
S. Arash Ostadzadeh, B. Maryam Elahi, Zeinab Zeinalpour, M. Amir Moulavi, Koen Bertels, A Two-phase Practical Parallel Algorithm for Construction of Huffman Codes., PDPTA 2007: 284-291
S. Bartolini, P. Foglia, C. A. Prete, MEmory performance: DEaling with applications, systems and architecture, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
S. Corbetta, Fabrizio Ferrandi, Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto, Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System., ISVLSI 2007: 457-458
S. Estévez-Martín, A. J. Fernández, T. Hortalá-González, M. Rodríguez-Artalejo, F. Sáenz-Pérez, R. del Vado-Vírseda, A Proposal for the Cooperation of Solvers in Constraint Functional Logic Programming, Electronic Notes in Theoretical Computer Science (ENTCS) , Volume 188, Elsevier Science Publishers B. V., July 2007
S. Shervin Ostadzadeh, Fereidoon Shams Aliee, S. Arash Ostadzadeh, An MDA-Based Generic Framework to Address Various Aspects of Enterprise Architecture., SCSS (1) 2007: 455-460
Sabine Glesner, Jens Knoop, Rolf Drechsler, Preface., Electr. Notes Theor. Comput. Sci. 190(4): 1-2 (2007)
Sabri Pllana, Ivona Brandic, Siegfried Benkner, Performance Modeling and Prediction of Parallel and Distributed Computing Systems: A Survey of the State of the Art., CISIS 2007: 279-284
Safouan Taha, Ansgar Radermacher, Sébastien Gérard, Jean-Luc Dekeyser, MARTE: UML-based Hardware Design from Modelling to Simulation., FDL 2007: 274-279
Safouan Taha, Ansgar Radermacher, Sebastien Gerard, Jean-Luc Dekeyser, An Open Framework for Detailed Hardware Modeling., SIES 2007: 118-125
Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero, PPM Reduction on Embedded Memories in System on Chip., European Test Symposium 2007: 85-90
Salman A. Khan, Andries P. Engelbrecht, A new fuzzy operator and its application to topology design of distributed local area networks, Information Sciences: an International Journal , Volume 177 Issue 13, Elsevier Science Inc., July 2007
Salman Khan, Polychronis Xekalakis, John Cavazos, Marcelo Cintra, Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems., PACT 2007: 327-338
Salvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias, Multi-processor operating system emulation framework with thermal feedback for systems-on-chip., ACM Great Lakes Symposium on VLSI 2007: 311-316
Salvatore Carta, Andrea Alimonda, Alessandro Pisano, Andrea Acquaviva, Luca Benini, A control theoretic approach to energy-efficient pipelined computation in MPSoCs., ACM Trans. Embedded Comput. Syst. 6(4): (2007)
Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal, Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs., DAC 2007: 777-782
Sandro Bartolini, Cinzia Castagnini, Enrico Martinelli, Inclusion of a Montgomery Multiplier Unit into an Embedded Processor’s Datapath to Speed-up Elliptic Curve Cryptography., IAS 2007: 95-100
Sanna Määttä, Jari Nurmi, Experiences of Using Object Oriented Programming Methods in High Level Network-on-Chip and System-on-Chip Design., ReCoSoC 2007: 84-89
Sarah Thompson, Alan Mycroft, Abstract interpretation of combinational asynchronous circuits., Sci. Comput. Program. 64(1): 166-183 (2007)
Sasa Tomic, Adrián Cristal, Osman S. Unsal, Mateo Valero, Hardware Transactional Memory with Operating System Support HTMOS., Euro-Par Workshops 2007: 8-17
Sascha Uhrig, Jörg Mische, Theo Ungerer, An IP Core for Embedded Java Systems., SAMOS 2007: 263-272
Sascha Uhrig, Jörg Wiese, jamuth: an IP processor core for embedded Java real-time systems., JTRES 2007: 230-237
Sean Rul, Hans Vandierendonck, Koen De Bosschere, Function level parallelism driven by data dependencies, SIGARCH Computer Architecture News , Volume 35 Issue 1, ACM, March 2007
Sebastián Reyes, Camelia Muñoz-Caro, Alfonso Niño, Rosa M. Badia, José M. Cela, Performance of computationally intensive parameter sweep applications on Internet-based Grids of computers: the mapping of molecular potential energy hypersurfaces., Concurrency and Computation: Practice and Experience 19(4): 463-481 (2007)
Sebastian Schuster, Uwe Brinkschulte, Model-Driven Development of Ubiquitous Applications for Sensor-Actuator-Networks with Abstract State Machines., SEUS 2007: 527-536
Sergio Barrachina, Peter Benner, Enrique S. Quintana-Ortí, Efficient algorithms for generalized algebraic Bernoulli equations based on the matrix sign function., Numerical Algorithms 46(4): 351-368 (2007)
Sergio Romero, Maria A. Trenas, Eladio Gutierrez, Emilio L. Zapata, Locality-improved FFT implementation on a graphics processor, ISCGAV'07: Proceedings of the 7th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision, World Scientific and Engineering Academy and Society (WSEAS), August 2007
Sergio Saponara, Esa Petri, Marco Tonarelli, Iacopo Del Corona, Luca Fanucci, FPGA-based networking systems for high data-rate and reliable in-vehicle communications., DATE 2007: 480-485
Sergio Saponara, Luca Fanucci, Stefano Marsi, Giovanni Ramponi, Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing., J. Real-Time Image Processing 1(4): 267-283 (2007)
Seung Woo Son, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir, Alok N. Choudhary, Compiler-Directed Energy Optimization for Parallel Disk Based Systems., IEEE Trans. Parallel Distrib. Syst. 18(9): 1241-1257 (2007)
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun, A practical FPGA-based framework for novel CMP research., FPGA 2007: 116-125
Seyed Masoud Sadjadi, J. Martínez, T. Soldo, L. Atencio, Rosa M. Badia, Jorge Ejarque, Improving Separation of Concerns in the Development of Scientific Applications., SEKE 2007: 456-461
Shabnam Mirshokraie, Mojtaba Sabeghi, Mahmoud Naghibzadeh, Koen Bertels, Performance Evaluation of Real-Time Message Delivery in RDM Algorithm., ICNS 2007: 74
Shady Copty, Itai Jaeger, Yoav Katz, Michael Vinov, Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation., DAC 2007: 891-895
Shashi Kumar, Sanjeev Kumar, Prakash, Ravi Shankar, M. K. Tiwari, Shashi Bhushan Kumar, Prediction of flow stress for carbon steels using recurrent self-organizing neuro fuzzy networks., Expert Syst. Appl. 32(3): 777-788 (2007)
Shekhar Borkar, Norman P. Jouppi, Per Stenström, Microprocessors in the era of terascale integration., DATE 2007: 237-242
Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry, Chris Wilkerson, Scheduling threads for constructive cache sharing on CMPs., SPAA 2007: 105-115
Shinichi Yamagiwa, Leonel Sousa, Design and implementation of a stream-based distributedcomputing platform using graphics processing units., Conf. Computing Frontiers 2007: 197-204
Shinichi Yamagiwa, Leonel Sousa, Caravela: A Novel Stream-Based Distributed Computing Environment., IEEE Computer 40(5): 70-77 (2007)
Shinichi Yamagiwa, Leonel Sousa, Diogo Antão, Data buffering optimization methods toward a uniform programming interface for gpu-based applications., Conf. Computing Frontiers 2007: 205-212
Shinichi Yamagiwa, Leonel Sousa, Tomás Brandão, Meta-Pipeline: A New Execution Mechanism for Distributed Pipeline Processing., ISPDC 2007: 17-24
Shun Long, Grigori Fursin, Björn Franke, A Cost-Aware Parallel Workload Allocation Approach Based on Machine Learning Techniques., NPC 2007: 506-515
Sid Ahmed Ali Touati, On the Periodic Register Need in Software Pipelining., IEEE Trans. Computers 56(11): 1493-1504 (2007)
Siham Tabik, Jesús M. Vías, Emilio L. Zapata, Luis F. Romero, Fast Insolation Computation in Large Territories., International Conference on Computational Science (1) 2007: 54-61
Silvia Rueda, Pedro Morillo, Juan M. Orduña, A Peer-To-Peer platform for simulating distributed virtual environments., ICPADS 2007: 1-8
Silvia Rueda, Pedro Morillo, Juan M. Orduña, José Duato, On the Characterization of Peer-To-Peer Distributed Virtual Environments., VR 2007: 107-114
Silvia Rueda, Pedro Morillo, Juan M. Orduña, José Duato, A genetic approach for adding QoS to distributed virtual environments., Computer Communications 30(4): 731-739 (2007)
Silvia Rueda, Pedro Morillo, Juan M. Orduna, A Saturation Avoidance Technique for Peer-to-Peer Distributed Virtual Environments, CW '07: Proceedings of the 2007 International Conference on Cyberworlds, IEEE Computer Society, October 2007
Simon Kluyskens, Lieven Eeckhout, Branch History Matching: Branch Predictor Warmup for Sampled Simulation., HiPEAC 2007: 153-167
Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini, Reducing Interconnect Cost in NoC through Serialized Asynchronous Links., NOCS 2007: 219
Simone Medardoni, Davide Bertozzi, Enrico Macii, Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies., ISLPED 2007: 159-164
Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto, Interactive presentation: Capturing the interaction of the communication memory and I/O subsystems in memory-centric industrial MPSoC platforms., DATE 2007: 660-665
Soledad Escolar, Jesús Carretero, Florin Isaila, Félix García Carballeira, A driver model based on Linux for TinyOS., SIES 2007: 361-364
Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich, Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS 2007 Salzburg Austria September 30 - October 3 2007, ACM 2007
Spiros Antonatos, Kostas Anagnostakis, Evangelos Markatos, Honey@home: a new approach to large-scale threat monitoring, WORM '07: Proceedings of the 2007 ACM workshop on Recurring malcode, ACM, November 2007
Spyros Antonatos, Periklis Akritidis, Evangelos P. Markatos, Kostas G. Anagnostakis, Defending against hitlist worms using network address space randomization., Computer Networks 51(12): 3471-3490 (2007)
Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen Boyd, Giovanni De Micheli, Temperature-aware processor frequency assignment for MPSoCs using convex optimization., CODES+ISSS 2007: 111-116
Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo, Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors., IEEE Trans. VLSI Syst. 15(8): 869-880 (2007)
Srinivasan Murali, Luca Benini, Giovanni De Micheli, An Application-Specific Design Methodology for On-Chip Crossbar Generation., IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1283-1296 (2007)
Stamatis Vassiliadis, Filipa Duarte, Stephan Wong, A Load/Store Unit for a Memcpy Hardware Accelerator., FPL 2007: 537-541
Stamatis Vassiliadis, Ioannis Sourdis, FLUX interconnection networks on demand., Journal of Systems Architecture 53(10): 777-793 (2007)
Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen, Embedded Computer Systems: Architectures Modeling and Simulation 7th International Workshop SAMOS 2007 Samos Greece July 16-19 2007 Proceedings, Springer 2007
Stefan Farfeleder, Andreas Krall, R. Nigel Horspool, Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures., Journal of Systems Architecture 53(8): 501-510 (2007)
Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, HySim: a fast simulation framework for embedded software development., CODES+ISSS 2007: 75-80
Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations., DATE 2007: 1349-1354
Stefan Raaijmakers, Stephan Wong, Run-time Partial Reconfiguration for Removal Placement and Routing on the Virtex-II-Pro., FPL 2007: 679-683
Stefano Baraldi, Alberto Del Bimbo, Lea Landucci, Nicola Torpei, Omar Cafini, Elisabetta Farella, Augusto Pieracci, Luca Benini, Introducing tangerine: a tangible interactive natural environment., ACM Multimedia 2007: 831-834
Stefano Ceri, Cristiana Bolchini, Daniele Braga, Marco Brambilla, Alessandro Campi, Sara Comai, Piero Fraternali, Pier Luca Lanzi, Marco Masseroli, Maristella Matera, Mauro Negri, Giuseppe Pelagatti, , Data and web management research at Politecnico di Milano., SIGMOD Record 36(4): 43-48 (2007)
Stephane Piskorski, Lionel Lacassagne, Samir Bouaziz, Daniel Etiemble, Customizing CPU instructions for embedded vision systems, ASAP '07: Proceedings of the 2007 IEEE International Conf. on Application-Specific Systems, Architectures and Processors (ASAP) - Volume 00 , Volume 00, IEEE Computer Society, July 2007
Stephen R. Schach, Tokunbo O. S. Adeshiyan, Daniel Balasubramanian, Gabor Madl, Esteban Osses, Sameer Singh, Karlkim Suwanmongkol, Minhui Xie, Dror G. Feitelson, Common coupling and pointer variables with application to a Linux case study., Software Quality Journal 15(1): 99-113 (2007)
Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton, A synthesizable datapath-oriented embedded FPGA fabric., FPGA 2007: 33-41
Stewart Massie, Nirmalie Wiratunga, Susan Craw, Alessandro Donati, Emmanuel Vicari, From Anomaly Reports to Cases., ICCBR 2007: 359-373
Stijn Eyerman, Lieven Eeckhout, A Memory-Level Parallelism Aware Fetch Policy for SMT Processors., HPCA 2007: 240-249
Stijn Eyerman, Lieven Eeckhout, James E. Smith, Studying Compiler-Microarchitecture Interactions through Interval Analysis., PACT 2007: 406
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith, A Top-Down Approach to Architecting CPI Component Performance Counters., IEEE Micro 27(1): 84-93 (2007)
Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis, Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement., Journal of Systems Architecture 53(7): 417-436 (2007)
Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor, Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns., DATE 2007: 1036-1041
Su-Shin Ang, George Constantinides, Wayne Luk, Peter Cheung, A Hybrid Memory Sub-system for Video Coding Applications, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk, Real-time hardware acceleration of the trace transform., J. Real-Time Image Processing 2(4): 235-248 (2007)
Sungroh Yoon, Luca Benini, Giovanni De Micheli, Co-clustering: A Versatile Tool for Data Analysis in Biomedical Informatics., IEEE Transactions on Information Technology in Biomedicine 11(4): 493-494 (2007)
Sutjipto Arifin, Peter Y. K. Cheung, A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information., ACM Multimedia 2007: 68-77
Sutjipto Arifin, Peter Y. K. Cheung, A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information., ICIP (6) 2007: 333-336
Sutjipto Arifin, Peter Y. K. Cheung, A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory"., ICSC 2007: 147-154
Suzanne Rivoire, Mehul A. Shah, Parthasarathy Ranganathan, Christos Kozyrakis, JouleSort: a balanced energy-efficiency benchmark., SIGMOD Conference 2007: 365-376
Suzanne Rivoire, Mehul A. Shah, Parthasarathy Ranganathan, Christos Kozyrakis, Justin Meza, Models and Metrics to Enable Energy-Efficiency Optimizations., IEEE Computer 40(12): 39-48 (2007)
Sven Karlsson, Stavros Passas, George Kotsis, Angelos Bilas, MultiEdge: An Edge-based Communication Subsystem for Scalable Commodity Servers., IPDPS 2007: 1-10
Sven Verdoolaege, Rachid Seghir, Kristof Beyls, Vincent Loechner, Maurice Bruynooghe, Counting Integer Points in Parametric Polytopes Using Barvinok's Rational Functions., Algorithmica 48(1): 37-66 (2007)
Sven-Arne Reinemo, Tor Skeie, Effective Shortest Path Routing for Gigabit Ethernet., ICC 2007: 6419-6424
T. Dias, S. Momcilovic, N. Roma, L. Sousa, Adaptive motion estimation processor for autonomous video devices, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Taewhan Kim, Pascal Sainrat, Steven S. Lumetta, Nacho Navarro, Proceedings of the 2007 International Conference on Compilers Architecture and Synthesis for Embedded Systems CASES 2007 Salzburg Austria September 30 - October 3 2007, ACM 2007
Talal Bonny, Jörg Henkel, Instruction splitting for efficient code compression, DAC '07: Proceedings of the 44th annual conference on Design automation, ACM, June 2007
Talal Bonny, Joerg Henkel, Efficient code density through look-up table compression, DATE '07: Proceedings of the conference on Design, automation and test in Europe, EDA Consortium, April 2007
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, Energy saving through a simple load control mechanism, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, Runahead Threads: Reducing Resource Contention in SMT Processors., PACT 2007: 423
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, Taj Muhammad Khan, Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor., ISPA 2007: 104-112
Tarik Saidani, Stéphane Piskorski, Lionel Lacassagne, Samir Bouaziz, Parallelization schemes for memory optimization on the cell processor: a case study of image processing algorithm, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Taylan Yemliha, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir, Vijay Degalahal, Compiler-Directed Code Restructuring for Operating with Compressed Arrays., VLSI Design 2007: 221-226
Teemu Pitkänen, Tero Partanen, Jarmo Takala, Low-Power Twiddle Factor Unit for FFT Computation., SAMOS 2007: 65-74
Tero Arpinen, Mikko Setälä, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Modeling Embedded Software Platforms with a UML Profile., FDL 2007: 237-242
Terrence S. T. Mak, K. P. Lam, H. S. Ng, G. Rachmuth, C.-S. Poon, A Current-Mode Analog Circuit for Reinforcement Learning Problems., ISCAS 2007: 1301-1304
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam, A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing., NOCS 2007: 173-182
Tessa E. Pronk, Andy D. Pimentel, Marco Roos, Timo M. Breit, Taking the example of computer systems engineering for the analysis of biological cell systems., Biosystems 90(3): 623-635 (2007)
Tessa E. Pronk, Simon Polstra, Andy D. Pimentel, Timo M. Breit, Evaluating the Design of Biological Cells Using a Computer Workbench., Annual Simulation Symposium 2007: 88-98
Théodore Marescaux, Erik Brockmeyer, Henk Corporaal, The Impact of Higher Communication Layers on NoC Supported MP-SoCs., NOCS 2007: 107-116
Théodore Marescaux, Henk Corporaal, Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT., DAC 2007: 116-121
Thilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich, Design space exploration of reliable networked embedded systems., Journal of Systems Architecture 53(10): 751-763 (2007)
Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg, Strategies for Compiling µ TC to Novel Chip Multiprocessors., SAMOS 2007: 127-138
Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos, Mechanisms for store-wait-free multiprocessors., ISCA 2007: 266-277
Thomas Fahringer, Christoph Anthes, Alexis Arragon, Arton Lipaj, Jens Müller-Iden, Christopher J. Rawlings, Radu Prodan, Mike Surridge, The edutain@grid Project., GECON 2007: 182-187
Thomas J. Ashby, Anthony D. Kennedy, Stephen M. Watt, Generation and optimisation of code using coxeter lattice paths., PASCO 2007: 1-10
Thomas Piquet, Olivier Rochecouste, André Seznec, Exploiting Single-Usage for Effective Memory Management., Asia-Pacific Computer Systems Architecture Conference 2007: 90-101
Thuy Duong Vu, Chris R. Jesshope, Formalizing SANE Virtual Processor in Thread Algebra., ICFEM 2007: 345-365
Tiago Dias, Nuno Roma, Leonel Sousa, Miguel Ribeiro, Reconfigurable architectures and processors for real-time video motion estimation., J. Real-Time Image Processing 2(4): 191-205 (2007)
Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero, Transactional Memory: An Overview., IEEE Micro 27(3): 8-29 (2007)
Tim Harris, Satnam Singh, Feedback directed implicit parallelism., ICFP 2007: 251-264
Tim Kindberg, Timothy Jones, \"Merolyn the Phone\": A Study of Bluetooth Naming Practices (Nominated for the Best Paper Award)., Ubicomp 2007: 318-335
Tim Todman, Wayne Luk, Domain Specific Transformations for Hardware Ray Tracing., CPA 2007: 479-492
Timo Alho, Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen, Compact hardware design of Whirlpool hashing core., DATE 2007: 1247-1252
Timo Alho, Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen, Compact modular exponentiation accelerator for modern FPGA devices., Computers & Electrical Engineering 33(5-6): 383-391 (2007)
Timo D. Hämäläinen, Stephan Wong, John Glossner, Stamatis Vassiliadis, Editorial., Journal of Systems Architecture 53(10): 677-678 (2007)
Timo Vanhatupa, Marko Hännikäinen, Timo D. Hämäläinen, Evaluation of throughput estimation models and algorithms for WLAN frequency planning., Computer Networks 51(11): 3110-3124 (2007)
Timo Viero, Kim Rounioja, Teemu Sipilä, Raimo Verkasalo, Jarmo Takala, Jorma Lilleberg, Dual Antenna Receivers for High Data Rate Terminals, Wireless Personal Communications: An International Journal , Volume 43 Issue 2, Kluwer Academic Publishers, October 2007
Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Tobias Schumacher, Enno Lübbers, Paul Kaufmann, Marco Platzner, Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster., PARCO 2007: 749-756
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney, Understanding Measurement Perturbation in Trace-based Data., IPDPS 2007: 1-6
Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan, Time Interpolation: So Many Metrics So Few Registers., MICRO 2007: 286-300
Tom Vander Aa, Bing-Feng Mei, Bjorn De Sutter, A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots, CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, ACM, September 2007
Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter, A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots., CASES 2007: 229-237
Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Friedbert Berens, Andreas Ruegg, A Survey on LDPC Codes and Decoders for OFDM-based UWB Systems., VTC Spring 2007: 1549-1553
Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci, Low complexity LDPC code decoders for next generation standards., DATE 2007: 331-336
Tsenka Stoyanova, Fotis Kerasiotis, Aggeliki S. Prayati, George Papadopoulos, Evaluation of impact factors on RSS accuracy for localization and tracking applications., MOBIWAC 2007: 9-16
Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala, Stride Permutation Networks for Array Processors., VLSI Signal Processing 49(1): 51-71 (2007)
Utpal Banerjee, José Moreira, Michel Dubois, Per Stenström, Proceedings of the 4th Conference on Computing Frontiers 2007 Ischia Italy May 7-9 2007, ACM 2007
Uwe Brinkschulte, Mathias Pacher, Alexander von Renteln, Towards an Artificial Hormone System for Self-organizing Real-Time Task Allocation., SEUS 2007: 339-347
Uwe Brinkschulte, Sunggu Lee, Editorial., Real-Time Systems 36(1-2): 1-2 (2007)
Víctor H. Escobar-Jeria, María J. Martín-Bautista, Daniel Sánchez, María-Amparo Vila, Web Usage Mining Via Fuzzy Logic Techniques, IFSA '07: Proceedings of the 12th international Fuzzy Systems Association world congress on Foundations of Fuzzy Logic and Soft Computing, Springer-Verlag, June 2007
Valentin Puente, José-Ángel Gregorio, Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks., IEEE Trans. Parallel Distrib. Syst. 18(6): 776-788 (2007)
Valery Sklyarov, Iouliia Skliarova, Encoding Algorithms for Logic Synthesis., AICCSA 2007: 359-366
Valery Sklyarov, Iouliia Skliarova, Reuse Technique in Hardware Design., IRI 2007: 36-41
Valery Sklyarov, Iouliia Skliarova, Manuel Almeida, Bruno Figueiredo Pimentel, A prototyping system for mobile devices., IWCMC 2007: 505-510
Vanderlei Bonato, Rafael Peron, Denis F. Wolf, José A. M. de Holanda, Eduardo Marques, João M. P. Cardoso, An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics., SIES 2007: 148-155
Vassilis Dimopoulos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems., ICSAMOS 2007: 186-193
Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis, Prototyping Efficient Interprocessor Communication Mechanisms., ICSAMOS 2007: 26-33
Vassos Soteriou, Li-Shiuan Peh, Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks., IEEE Trans. Parallel Distrib. Syst. 18(3): 393-408 (2007)
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh, Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks., IEEE Trans. VLSI Syst. 15(8): 855-868 (2007)
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh, Software-directed power-aware interconnection networks., TACO 4(1): (2007)
Veerle Desmet, Hans Vandierendonck, Koen De Bosschere, Clustered indexing for branch predictors., Microprocessors and Microsystems 31(3): 168-177 (2007)
Vicenç Beltran, Jordi Torres, Eduard Ayguadé, Improving disk bandwidth-bound applications through main memory compression, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Vijayanand Nagarajan, Rajiv Gupta, Matias Madou, Xiangyu Zhang, Bjorn De Sutter, Matching Control Flow of Program Versions., ICSM 2007: 84-93
Vincenzo Catania, Maurizio Palesi, Davide Patti, Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario., Journal of Circuits Systems and Computers 16(5): 819-846 (2007)
Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto, An adaptive genetic algorithm for dynamically reconfigurable modules allocation., VLSI-SoC 2007: 128-133
Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Dynamic Reconfigurability in Embedded System Design., ISCAS 2007: 2734-2737
Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert, Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux., IPDPS 2007: 1-8
Vitaliy Tykhomyrov, Alexander Sayenko, Henrik Martikainen, Olli Alanen, Timo Hämäläinen, Performance Evaluation of the IEEE 802.16 ARQ Mechanism., NEW2AN 2007: 148-161
W. A. Rajitha Jayaruwan Weerakkody, Warnakulasuriya Anil Chandana Fernando, José Luis Martínez, Pedro Cuenca, Francisco J. Q