Dear colleague,

BSC-DAC-UPC invite you to attend on-line the following talk:

-Title: Stochastic Model of Robust Resource Management for Heterogeneous Parallel Computing Systems
-Speaker: H. J. Siegel (Department of Electrical and Computer Engineering and Department of Computer Science, Colorado State University)
-Date: Wed 21, 11:00 CET
-How to follow the talk on-line: http://www.ac.upc.edu/seminars

If you would like to ask questions to the speaker, please send an e-mail to seminar@hipeac.ac.upc.edu

Best regards,

Enric Morancho

P.S.:
Repository of HIPEAC on-line video seminars: http://hipeac.ac.upc.edu/seminars/ and http://www.hipeac.net/recorded_seminars

Abstract

What does it mean for a computer system to be robust? How can robustness be described? How does one determine if a claim of robustness is true? How can one decide which of two systems is more robust? Parallel computing systems are often heterogeneous mixtures of machines, used to execute collections of tasks with diverse computational requirements. A critical research problem is how to allocate resources to tasks to optimize some performance objective. However, systems frequently have degraded performance due to uncertainties, such as inaccurate estimates of actual workload parameters. It is important for system performance to be robust against uncertainty. To accomplish this, we present a stochastic model for deriving the robustness of a resource allocation. This model assumes that stochastic (experiential) information is available for a parameter whose actual values are uncertain. The robustness of a resource allocation is quantified as the probability that a user-specified level of system performance can be met. We show how to use this stochastic model to evaluate the robustness of resource assignments and to design resource management heuristics that produce robust allocations. The stochastic robustness analysis approach can be applied to a variety of computing and communication system environments, including parallel, distributed, cluster, grid, Internet, cloud, embedded, multicore, content distribution networks, wireless networks, and sensor networks. Furthermore, the robustness model is generally applicable to design problems throughout various scientific and engineering fields.

Bio

H. J. Siegel is the George T. Abell Endowed Chair Distinguished Professor of Electrical and Computer Engineering at Colorado State University (CSU), where he is also a Professor of Computer Science. He is Director of the CSU Information Science and Technology Center (ISTeC), a university-wide organization for enhancing CSUs activities pertaining to the design and innovative application of computer, communication, and information systems. Before joining CSU, he was a Professor at Purdue University from 1976 to 2001. He received two B.S. degrees from the Massachusetts Institute of Technology (MIT), and the M.A., M.S.E., and Ph.D. degrees from Princeton University. He is a Fellow of the IEEE and a Fellow of the ACM. Prof. Siegel has co-authored over 380 published technical papers in the areas of parallel and distributed computing. He was a Coeditor-in-Chief of the Journal of Parallel and Distributed Computing, and was on the Editorial Boards of the IEEE Transactions on Parallel and Distributed Systems and the IEEE Transactions on Computers.

Dear colleague,

BSC-DAC-UPC invite you to attend on-line the following talk:

-Title: Value Prediction in Parallel Architectures
-Speaker: Jean-Luc Gaudiot (Department of Electrical Engineering and Computer Science, University of California)
-Date: Mon 26, 11:00 CET
-How to follow the talk on-line: http://www.ac.upc.edu/seminars

If you would like to ask questions to the speaker, please send an e-mail to seminar@hipeac.ac.upc.edu

Best regards,

Enric Morancho

P.S.:
Repository of HIPEAC on-line video seminars: http://www.hipeac.net/recorded_seminars

Abstract

The newly emerging many-core-on-a-chip designs have renewed an intense interest in parallel processing. By applying Amdahls formulation to the programs in the PARSEC and SPLASH-2 benchmark suites, we find that most applications may not have sufficient parallelism to efficiently utilize modern parallel machines. The long sequential portions in these application programs are caused by computation as well as communication latency. However, value prediction techniques may allow the parallelization of the sequential portion by predicting values before they are produced. In conventional superscalar architectures, the computation latency dominates the sequential sections. Thus value prediction techniques may be used to predict the computation result before it is produced. In many-core architectures, since the communication latency increases with the number of cores, value prediction techniques may be used to reduce both the communication and computation latency. We extend these ideas by using GPUs to accelerate programs that contain limited parallelism and those that are hard to parallelize.

Bio

Professor Jean-Luc Gaudiot received the Diplôme d'Ingénieur from the École Supérieure d'Ingénieurs en Electronique et Electrotechnique, Paris, France in 1976 and the M.S. and Ph.D. degrees in Computer Science from the University of California, Los Angeles in 1977 and 1982, respectively.

He is currently a Professor in the Electrical Engineering and Computer Science Department at the University of California, Irvine. He was Chair of the Department from 2003 to 2009. During his tenure, the department underwent significant changes. These include the hiring of twelve new faculty members (three senior professors) and the remarkable rise in the US News and World Report® rankings of the Computer Engineering program from 42 to 28 (46 to 36 for the Electrical Engineering program).

Prior to joining UCI in January 2002, he was a Professor of Electrical Engineering at the University of Southern California since 1982, where he served as Director of the Computer Engineering Division for three years. He has also designed distributed microprocessor systems at Teledyne Controls, Santa Monica, California (1979-1980) and performed research in innovative architectures at the TRW Technology Research Center, El Segundo, California (1980-1982). He frequently acts as consultant to companies that design high-performance computer architectures, and has served as an expert witness in patent infringement and product liability cases. His research interests include multithreaded architectures, fault-tolerant multiprocessors, and implementation of reconfigurable architectures. He has published over 200 journal and conference papers. His research has been sponsored by NSF, DoE, and DARPA, as well as a number of industrial organizations.

In January 2006, he became the first Editor-in-Chief of the IEEE Computer Architecture Letters, a new publication of the IEEE Computer Society, which he helped found to the end of facilitating short, fast turnaround of fundamental ideas in the Computer Architecture domain. From 1999 to 2002, he was the Editor-in-Chief of the IEEE Transactions on Computers. In June 2001, he was elected chair of the IEEE Technical Committee on Computer Architecture, and re-elected in June 2003 for a second two-year term.

Dr. Gaudiot is a member of AAAS, ACM, and IEEE. He has also chaired the IFIP Working Group 10.3 (Concurrent Systems). He was co-General Chairman of the 1992 International Symposium on Computer Architecture, Program Committee Chairman of the 1993 IFIP Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, the 1993 IEEE Symposium on Parallel and Distributed Processing (Systems Track), the 1995 Parallel Architectures and Compilation Techniques Conference (PACT 95), the High Performance Computer Architecture conference in 1999 (HPCA-5), and the 2005 International Parallel and Distributed Processing Symposium.

In 1999, he became a Fellow of the IEEE, For Contributions to the Programmability and Reliability of Dataflow Architectures. He was elevated to the rank of AAAS Fellow in 2007, For Distinguished Contributions to the Design and Analysis of Highly Efficient Multiprocessor and Memory System Architectures.

Dr. Gaudiot is an avid pilot and he brings to his leisure time his love for teaching by being a flight instructor (both primary and instrument).

http://pascal.eng.uci.edu/people/gaudiot.html

Dear colleague,

BSC-DAC-UPC invite you to attend on-line the following talk:

-Title: Portable, Scalable, per-Core Power Estimation for Intelligent Resource Management
-Speaker: Sally A. McKee (Chalmers University of Technology)
-Date: Wed 2, 10:00 CET
-How to follow the talk online: http://www.fib.upc.edu/sala-actes

If you would like to ask questions to the speaker, please send an e-mail to seminar@hipeac.ac.upc.edu

Best regards,

Enric Morancho

P.S.:
Repository of HIPEAC on-line video seminars: http://www.hipeac.net/recorded_seminars

---

Abstract

Power and temperature have joined performance as first-order design
constraints. Balancing power efficiency, thermal constraints, and performance
requires some means to convey data about real-time power consumption and
temperature to intelligent resource managers.

Resource managers can use this information to meet performance goals, maintain
power budgets, and obey thermal constraints. Unfortunately, obtaining the
required machine introspection is challenging. Most current chips provide no
support for per-core power monitoring, and when support exists, it is not
exposed to software.

We present a methodology for deriving per-core power models using sampled
performance counter values and temperature sensor readings. We develop
accurate, application-independent models for several CMPs, and show how they
can be used to guide scheduling decisions in power-aware resource managers
enforcing a specified power envelope.

Bio

http://www.csl.cornell.edu/~sam/

Dear colleague,

BSC-DAC-UPC invite you to attend on-line the following talk:

-Title: Efficient Resource Management for Large Scale Parallelism
-Speaker: Christos Kozyrakis (Stanford University)
-Date: Mon 26, 12:00 CET

How to follow the talk on-line: http://www.ac.upc.edu/seminars

If you would like to ask questions to the speaker, please send an e-mail to seminar@hipeac.ac.upc.edu

Best regards,

Enric Morancho

Efficient Resource Management for Large Scale Parallelism
Christos Kozyrakis (Stanford University)

Abstract

Multi-core chips will soon include hundreds of cores, support thousands of hardware threads, and feature deep memory hierarchies with non-uniform latency characteristics. To maximize efficiency from such systems, we must carefully manage resources (cores, memory, and interconnect) in a manner that balances performance and power consumption, improves both load balance and locality, and minimizes management overheads.

This talk will present early work on resource management for large-scale multi-core systems at the Pervasive Parallelism Lab (PPL) in Stanford University. PPL is investigating software and hardware techniques for pervasive parallelism based on programs written in domain specific languages (DSLs). First, we will discuss how to scale a user-level runtime environment for a DSL to hundreds of cores and NUMA latencies. We will show that by carefully reconsidering the algorithms and data-structures, we can improve speedup by up to 19x for highly parallel applications. Second, we will discuss separation of functions and interfaces between user-level runtimes and the operating system. We will also show how to overcome scalability issues in virtual memory operations for shared-memory operating systems like Linux. Finally, we will describe simple hardware support for fine-grain parallelism that allows for the development of low-overhead, software-mostly runtime systems that scale efficiently to hundreds of hardware threads. We will show that the proposed runtimes can exceed the performance of hardware-only scheduling by up to a factor of 2x.

Bio

Christos Kozyrakis is an Associate Professor of Electrical Engineering & Computer Science at Stanford University. He received a BS degree from the University of Crete (Greece) and a PhD degree from the University of California at Berkeley (USA), both in Computer Science.

Christos works on architectures, runtime environments, and programming models for parallel computer systems. At Berkeley, he developed the IRAM architecture, a novel media-processor system that combined vector processing with embedded DRAM technology. At Stanford, he lead the Transactional Coherence and Consistency (TCC) project at Stanford that developed hardware and software mechanisms for programming with transactional memory. He has also investigated security systems and power management techniques for data-centers. Currently, he is a member of the Pervasive Parallelism Lab, a multi-faculty effort to make parallel computing practical for the masses.

Christos is the Willard R. and Inez Kerr Bell faculty scholar at Stanford University. He is also a senior member of the ACM and the IEEE. He has received the NSF Career Award, an IBM Faculty Award, the Okawa Fundantion Research Grant, and a Noyce Family Faculty Scholarship.