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<div class=Section1>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US
style='font-size:14.0pt'>Rapid Simulation and Performance Evaluation: <o:p></o:p></span></b></p>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US
style='font-size:14.0pt'>Methods and Tools <o:p></o:p></span></b></p>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US
style='font-size:14.0pt'>(RAPIDO’09)<o:p></o:p></span></b></p>
<p class=Default align=center style='text-align:center'><b><a
href="http://www2.lifl.fr/rapido09"><span lang=EN-US>http://www2.lifl.fr/rapido09</span></a></b><b><span
lang=EN-US><o:p></o:p></span></b></p>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US><o:p> </o:p></span></b></p>
<p class=Default align=center style='text-align:center'><span lang=EN-US
style='font-family:"Calibri","sans-serif"'>In conjunction with the 4th International
Hipeac conference.<o:p></o:p></span></p>
<p class=Default align=center style='text-align:center'><span lang=EN-US
style='font-family:"Calibri","sans-serif"'>Paphos, Cyprus, January 25, 2009<o:p></o:p></span></p>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US
style='font-family:"Calibri","sans-serif"'><o:p> </o:p></span></b></p>
<p class=Default align=center style='text-align:center'><b><i><u><span
lang=EN-US style='font-size:14.0pt;font-family:"Calibri","sans-serif"'>Program
and Call for Participation<o:p></o:p></span></u></i></b></p>
<p class=MsoNormal style='text-autospace:none'><b><span lang=EN-US
style='font-size:12.0pt;color:black'>Scope<o:p></o:p></span></b></p>
<p class=MsoNormal style='text-autospace:none'><span lang=EN-US
style='font-size:12.0pt;color:black'>The purpose of Rapido’09 is to bring
researchers and practitioners from the communities of embedded systems and
general purpose systems together to explore and discuss recent progress in the
area of simulation and performance evaluation techniques and tools. In the
first part of the workshop, in-depth technology challenges and state-of-the-art
research presentations will be given by 5 R&D actors from academia and
industry. In the second part, 7 selected research papers will be presented.<o:p></o:p></span></p>
<p class=MsoNormal style='text-autospace:none'><span lang=EN-US
style='font-size:12.0pt;color:black'><o:p> </o:p></span></p>
<p class=MsoNormal style='text-autospace:none'><b><span lang=EN-US
style='font-size:12.0pt;color:#1F497D'>Organizers </span></b><b><span
lang=EN-US style='font-size:12.0pt;color:black'><o:p></o:p></span></b></p>
<p class=MsoNormal style='text-autospace:none'><span lang=EN-US
style='font-size:12.0pt;color:black'>Smail Niar, University of Valenciennes and
INRIA, France, Smail.Niar@inria.fr<o:p></o:p></span></p>
<p class=MsoNormal style='text-autospace:none'><span lang=EN-US
style='font-size:12.0pt;color:black'>Rainer Leupers, Aachen University,
Germany, leupers@iss.rwth-aachen.de<o:p></o:p></span></p>
<p class=MsoNormal style='text-autospace:none'><span lang=EN-US
style='font-size:12.0pt;color:black'>Olivier Temam, INRIA, France,
Olivier.Temam@inria.fr<o:p></o:p></span></p>
<p class=Default><span lang=EN-US style='font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
<p class=Default><b><span lang=EN-US style='font-family:"Calibri","sans-serif"'>Advanced
Program<o:p></o:p></span></b></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US
style='font-family:"Calibri","sans-serif"'>INVITED SPEAKERS<o:p></o:p></span></b></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>09:00:
SimFlex & ProtoFlex: Full-System Emulators/Simulators for Large-Scale
Multiprocessors<o:p></o:p></span></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
<i>Babak Falsafi</i>, EPFL, Lausanne (Invited Speaker)<o:p></o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>09:45:
Performance Density Exploration of Heterogeneous Multicore Architectures<o:p></o:p></span></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Andrei Terechko</span></i><span
lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>, NXP,
Eindhoven, the Netherlands (Invited Speaker)<o:p></o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>10:30
Break<o:p></o:p></span></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default style='text-indent:35.4pt'><span lang=EN-US style='font-size:
11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>11:00
Architecture Exploration through Ultra-Fast Simulation<o:p></o:p></span></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Nigel Topham</span></i><span
lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>, University
of Edinburgh, UK (Invited Speaker)<o:p></o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>11:45
Simulation and Validation: Challenges in Wireless Baseband Processing <o:p></o:p></span></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Norbert Wehn</span></i><span
lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>, TU
Kaiserslautern, Germany (Invited Speaker)<o:p></o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>12:30
Lunch<o:p></o:p></span></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default style='text-indent:35.4pt'><span lang=EN-US style='font-size:
11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>14:30
Know Before You Go: The Rise of System Level Simulation<o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Giovanni Beltrame</span></i><span
lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>,
European Space Agency, the Netherlands (Invited Speaker)<o:p></o:p></span></p>
<div style='border:none;border-top:solid windowtext 1.0pt;padding:1.0pt 0cm 0cm 0cm'>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US
style='font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></b></p>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></b></p>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US
style='font-family:"Calibri","sans-serif"'>RESEARCH PAPERS<o:p></o:p></span></b></p>
<p class=Default align=center style='text-align:center'><b><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></b></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>15:15
Fast and Accurate Simulation Using the LLVM Compiler Framework<o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>F. Brandner, A.
Fellnhofer, A.S. Krall, and D.Riegler</span></i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> (Vienna University
of Technology, Austria)<o:p></o:p></span></p>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>15:35
Integration of Power Saving Techniques in the UNISIM Simulation Framework
through the <o:p></o:p></span></p>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
Shadow Module Design Paradigm<o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>D. Ludovici, G.
Keramidas, G.N. Gaydadjiev and S. Kaxiras </span></i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p>
<p class=Default style='margin-left:35.4pt;text-indent:35.4pt'><span
lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>(Delft
University of Technology, The Netherlands And University of Patras, Greece)<o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><span lang=EN-US style='font-size:
11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
<div style='border-top:solid windowtext 1.0pt;border-left:none;border-bottom:
solid windowtext 1.0pt;border-right:none;padding:1.0pt 0cm 1.0pt 0cm'>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>15:55
Break<o:p></o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>16:30
System Level Modelling for SpiNNaker CMP System <o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>M.M. Khan, E.
Painkras, X. Jin, L.A. Plana, J.V. Woods and S.B. Furber</span></i><span
lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><span lang=EN-US style='font-size:
11.0pt;font-family:"Calibri","sans-serif"'>(The University of Manchester, UK)<o:p></o:p></span></p>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>16:50
System Level Performance Simulation for Heterogeneous Multi-Processor
Architectures<o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>M. Streubühr, C.
Haubelt, and J. Teich</span></i><span lang=EN-US style='font-size:11.0pt;
font-family:"Calibri","sans-serif"'> (University of Erlangen-Nuremberg,
Germany)<o:p></o:p></span></p>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>17:10
Rapid Transactional Level Simulation for Multiprocessor Systems<o:p></o:p></span></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>I. Assayad and S.
Yovine</span></i><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
(Verimag, University of Grenoble, France)<o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><span lang=EN-US style='font-size:
11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>17:30
Break<o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><span lang=EN-US style='font-size:
11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>17:50
A DoE/RSM-based Strategy for an Efficient Design Space Exploration Targeted to
CMPs<o:p></o:p></span></p>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
<i>G. Palermo, C. Silvano, and V. Zaccaria</i> (Politecnico di Milano,
Italy)<o:p></o:p></span></p>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>18:10
Improving Cycle-level Modular Simulation by Vectorization<o:p></o:p></span></p>
<p class=Default style='text-indent:35.4pt'><i><span lang=EN-US
style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>D. Parello, M.
Bouache, and B. Goossens</span></i><span lang=EN-US style='font-size:11.0pt;
font-family:"Calibri","sans-serif"'> (University of Perpignan, France)<o:p></o:p></span></p>
<div style='border:none;border-bottom:solid windowtext 1.0pt;padding:0cm 0cm 1.0pt 0cm'>
<p class=Default style='text-indent:35.4pt'><span lang=EN-US style='font-size:
11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
</div>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p>
<p class=Default><b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>REGISTRATION
<o:p></o:p></span></b></p>
<p class=Default><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>The
Rapido’09 workshop is affiliated with the 2009 Hipeac conference. To register
for the workshop, please visit: <a
href="http://www.hipeac.net/conference/index.php?form=form1"><span
style='color:black'>http://www.hipeac.net/conference/index.php?form=form1</span></a></span><span
lang=EN-US style='font-size:11.0pt'><o:p></o:p></span></p>
<p class=MsoNormal><o:p> </o:p></p>
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