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<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal align=center style='text-align:center'><span lang=EN-US
style='font-size:16.0pt;color:red'>1st Workshop on Rapid Simulation and
Performance Evaluation: Methods and Tools (RAPIDO’09)<o:p></o:p></span></p>
<p class=MsoNormal align=center style='text-align:center'><span lang=EN-US>Held
in conjunction with the 4th International Conference on High-Performance and<o:p></o:p></span></p>
<p class=MsoNormal align=center style='text-align:center'><span lang=EN-US>Embedded
Architectures and Compilers (HiPEAC)<o:p></o:p></span></p>
<p class=MsoNormal align=center style='text-align:center'><span lang=EN-US>Paphos,
Cyprus, January 25-28, 2009<o:p></o:p></span></p>
<p class=MsoNormal align=center style='text-align:center'><span lang=EN-US><a
href="http://www2.lifl.fr/rapido09/">http://www2.lifl.fr/rapido09/</a><o:p></o:p></span></p>
<p class=MsoNormal align=center style='text-align:center'><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Future-generation processors will integrate
numerous units on a single die, including multiple processor cores, multiple
levels of (shared/private) caches or memories, and multiple dedicated
accelerators, which will be glued together through a network on-chip (NoC).<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>In the embedded systems domain, the
Intellectual Property (IP) based design approach is one of the most popular
solutions to overcome this design challenge by relying on parameterized and
pre-designed IP cores. In the general-purpose computing domain, the
time-to-market is typically longer, the design is typically not limited to
interconnecting pre-existing IP cores, however, the design should be optimized
for a broader set of applications. In both the embedded and the general-purpose
domains, searching the huge design space during the design process is done
through Design Space Exploration (DSE). <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>DSE involves a number of key technologies
such as modeling, simulation, prototyping, heuristic searching, etc. which have
to cooperate in order to obtain a final design with an optimal
performance/power/cost/reliability without compromising the time-to-market. The
purpose of this workshop is to look deeper into these issues, and bring
researchers and practitioners from both communities (embedded systems and
general purpose computing) together to explore and discuss recent progress, and
stimulate the interaction between them through exchange of ideas and experience
sharing. <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>In the first part of the workshop, in-depth
technology challenges and state-of-the-art research presentations will be given
by key R&D actors from academia and industry. In the second part, selected
research papers will be presented.<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Topics of interest include, but are not
limited to: <o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
Rapid simulation techniques: sampled simulation, statistical simulation,
hardware-accelerated simulation (e.g., using FPGAs), fast full-system
simulation, parallel and distributed simulation, etc.<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
High-level abstraction modeling, e.g., Transactional Level Modeling (TLM)<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
Analytical modeling<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
Modeling and simulation techniques tailored towards multi-core and many-core
architectures and/or MPSoCs<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
Multi-program and multi-threaded workload generation and simulation<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
Smart exploration techniques and (meta)heuristics for DSE<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
Industrial tools for rapid system design and analysis<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
Experience reports using existing simulators<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
Simulator validation<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:35.4pt'><span lang=EN-US>•
Simulation and modeling techniques for multi-layer software (including OSes,
virtual machines, middleware and applications) running on future hardware<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Organizers : <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Smail Niar, INRIA Lille,
France Smail.Niar[at]inria.fr<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Rainer Leupers, Aachen University,
Germany
leupers[at]iss.rwth-aachen.de<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Olivier Temam, INRIA Orsay,
France
Olivier.Temam[at]inria.fr<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Important dates : <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Submission deadline: Nov 3, 2008<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Notification to authors:
Nov 28, 2008<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Final version of accepted
papers: Dec 19, 2008<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Paper submission: <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Submitted papers should use the LNCS format
and should be 6 pages maximum. <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>They must be sent to:
smail.niar[at]inria.fr. <o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US>Manuscript preparation guidelines can be found
at the LNCS specification web site (go to -> For Authors -> Information
for LNCS Authors).<o:p></o:p></span></p>
<p class=MsoNormal><o:p> </o:p></p>
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