<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div><blockquote type="cite"><div><div style="margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; min-height: 14px; "><span class="Apple-style-span" style="-webkit-text-stroke-width: -1; "><font class="Apple-style-span" size="5"><span class="Apple-style-span" style="font-size: 18px;">Call for participation</span></font></span></div></div><div style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><span class="Apple-style-span" style="font-family: Times; font-size: 14px; -webkit-border-horizontal-spacing: 10px; -webkit-border-vertical-spacing: 10px; "><h3 style="margin-right: 0in; margin-left: 0in; font-family: 'Times New Roman'; color: black; "><font class="Apple-style-span" face="Arial"><span class="Apple-style-span" style="font-weight: normal; "><font class="Apple-style-span" size="4"><span class="Apple-style-span" style="font-size: 14px;">Held in conjunction with PACT 2008 (<a href="http://www.eecg.toronto.edu/pact">http://www.eecg.toronto.edu/pact</a>)</span></font></span></font></h3><h3 style="margin-right: 0in; margin-left: 0in; font-family: 'Times New Roman'; color: black; "><font class="Apple-style-span" face="Arial"><span class="Apple-style-span" style="font-weight: normal; "><span class="Apple-style-span" style="font-family: 'Times New Roman'; font-weight: bold; "><span style="font-family: Tahoma; "><font class="Apple-style-span" size="4"><span class="Apple-style-span" style="font-size: 14px;">Toronto, </span></font><st1:place w:st="on"><st1:country-region w:st="on"><font class="Apple-style-span" size="4"><span class="Apple-style-span" style="font-size: 14px;">CANADA</span></font></st1:country-region></st1:place><font class="Apple-style-span" size="4"><span class="Apple-style-span" style="font-size: 14px;"> <br>Saturday October 25, 2008</span></font></span></span></span></font></h3><h3 style="margin-right: 0in; margin-left: 0in; font-size: 13.5pt; font-family: 'Times New Roman'; color: black; font-weight: bold; "><span class="Apple-style-span" style="font-family: Arial; font-size: 16px; "><span class="SpellE">SimFlex</span> and <span class="SpellE">ProtoFlex</span>: Fast, Accurate, and Flexible Full-System Simulation of Multicore/Multiprocessor Systems</span></h3><h3 style="margin-right: 0in; margin-left: 0in; font-size: 13.5pt; font-family: 'Times New Roman'; color: black; font-weight: bold; "><span style="font-size: 12pt; font-family: Arial; "><span class="Apple-style-span" style="font-family: 'Times New Roman'; font-weight: normal; "><a href="http://www.ece.cmu.edu/~simflex" style="color: blue; "><b><span style="font-size: 11pt; font-family: Arial; ">http://www.ece.cmu.edu/~simflex</span></b></a></span></span></h3><div style="text-align: center; margin-top: 0in; margin-right: 0in; margin-left: 0in; margin-bottom: 0.0001pt; font-size: 12pt; font-family: 'Times New Roman'; color: black; "><b><span style="font-size: 11pt; font-family: Arial; "><o:p> </o:p></span></b></div><div style="margin-top: 0in; margin-right: 0in; margin-left: 0in; margin-bottom: 0.0001pt; font-size: 12pt; font-family: 'Times New Roman'; color: black; "><span style="font-size: 10pt; font-family: Arial; color: windowtext; ">Computer architects have long relied on software simulation to evaluate the functionality and performance of architectural innovations. Unfortunately, modern <span class="SpellE">cycle-accurate</span> </span><span style="font-size: 10pt; font-family: Arial; ">simulators are several orders of magnitude slower than real hardware and the growing levels of hardware integration increase simulation complexity even further. In addition, conventional simulators are optimized for speed at the expense of code flexibility and maintainability. In this tutorial, we present the <span class="SpellE">SimFlex</span> and <span class="SpellE">ProtoFlex</span> family of simulation tools for fast, accurate, and flexible simulation of <span class="SpellE">uniprocessor</span>, multi-core and distributed shared-memory systems. <span class="SpellE">SimFlex </span>achieves fast simulation turnaround while ensuring representative results by leveraging the SMARTS simulation sampling framework. At the same time, its component-based design allows for easy composition of complex multi-core and multiprocessor systems. <span class="SpellE">ProtoFlex</span> is an FPGA-accelerated simulation technology that complements <span class="SpellE">SimFlex</span> by enabling full-system functional simulation of multiprocessor and multi-core systems at speeds of one to two orders of magnitude faster than software <span class="SpellE">tools.In</span> this <span class="GramE">tutorial,</span> first we introduce attendees to the SMARTS simulation sampling approach. We present relevant background from statistics and compare and contrast statistical sampling with other sampling proposals. Second, we present the design, implementation and use of the <span class="SpellE">Flexus</span> simulator suite. <span class="SpellE">Flexus</span> is a family of component based C++ architecture simulators that implement cycle-accurate models of multi-core and multiprocessor systems. We give attendees hands-on experience with <span class="SpellE">Sim</span>- Flex/<span class="SpellE">TraceFlex</span>, a <span class="SpellE">Flexus</span> model for fast functional and memory system simulation, <span class="SpellE">SimFlex/OoO</span>, a <span class="SpellE">Flexus</span> model for cycle-accurate simulation, and <span class="SpellE">Flexus</span>’ statistical managers and sampling tools. Finally, we present a hands-on technology preview of <span class="SpellE">ProtoFlex</span>. We give attendees the opportunity to compile, execute and profile multithreaded applications on a real operating system running on a BEE2 FPGA platform.</span></div></span></div></blockquote></div><br></body></html>