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<p><tt>****</tt><br>
<tt>**** The submission deadline has been extended to</tt><br>
<tt>**** SUNDAY July 6, 2008 (MIDNIGHT 23:59 CET)</tt><br>
<tt>****</tt><br>
<br>
<tt>[Please accept our apologies if you receive multiple copies of this Call <br>
For Papers]<br>
<br>
CALL FOR PAPERS IET Computers & Digital Techniques (Formerly IEE <br>
Proceedings Computers & Digital Techniques)<br>
<br>
============================<br>
Special Issue on Networks On Chip<br>
============================<br>
<br>
The most daunting challenge to future on-chip multiprocessor systems is <br>
to realise the enormous bandwidth capacities and stringent latency <br>
requirements when interconnecting a large number of processing cores in <br>
a power-efficient fashion. In a short time span, networks-on-chips have <br>
been recognised as the most important alternative for the design of <br>
modular and scalable communication architectures in the nanometre <br>
regime. This special issue intends to host relevant research <br>
contributions advancing knowledge in the field of on-chip networks. <br>
Submissions addressing design issues at all levels of abstraction are <br>
encouraged, from physical on-chip link design to data-link layer, from <br>
novel design-space exploration, ranging up to programming models and <br>
application software.<br>
<br>
Topics of interest include but are not limited to:<br>
====================================<br>
<br>
Network architecture (topology, routing, arbitration)<br>
Power and energy issues in NoCs application-specific NoC design<br>
Timing, synchronous/asynchronous communication<br>
NoC case studies, application-specific NoC design<br>
NoC reliability issues<br>
O/S support for NoC<br>
Metrics and benchmarks for NoCs<br>
NoC Network interface issues<br>
Modelling, simulation, and synthesis of NoCs<br>
Network-on-chip design methodologies<br>
NoC Quality of Service<br>
NoC support for CMP / MPSoC<br>
NoC support for memory access<br>
NoCs for FPGAs and structured ASIC<br>
Programming models<br>
Mapping of applications onto NoCs<br>
Novel interconnect links / switches /routers<br>
Signaling and circuit design for NoC links<br>
Physical design of interconnect and NoC<br>
NoC design tools<br>
Debug & Test of NoC<br>
Floorplan aware NoC architecture optimisation<br>
<br>
Submission details<br>
===============<br>
<br>
Authors are encouraged to submit high-quality research contributions <br>
that will not require major revisions. Extensions of paper presented at <br>
the International Symposium on Networks-on-Chip, Newcastle Upon Tyne, <br>
United Kingdom, April 7-10, 2008 (</tt><tt><a href="http://async.org.uk/nocs2008">http://async.org.uk/nocs2008</a></tt><tt>), are <br>
especially encouraged, but work not presented at the symposium is also <br>
welcome. Please identify clearly the additional material from the <br>
original symposium paper in your submitted manuscript. A minimum of 30% <br>
new material is required, including deeper theory or extensions of <br>
experimental results.<br>
<br>
Prospective authors should submit their manuscripts electronically via <br>
the IET CDT submission site: </tt><tt><a href="http://mc.manuscriptcentral.com/cdt">http://mc.manuscriptcentral.com/cdt</a></tt><tt>. <br>
Authors should clearly identify their papers as submissions for the <br>
Special Issue on Networks-on-Chip 2008 on their manuscript. All <br>
manuscripts are subject to the standard IET CDT review process. <br>
Instructions on how to submit a paper can be found at <br>
</tt><tt><a href="http://www.theiet.org/publications/journals/">http://www.theiet.org/publications/journals/</a></tt><tt> and authors can contact the <br>
journal's managing editor, Tony Donegan (tdonegan@theiet.org) , for <br>
further assistance.<br>
<br>
Guest Editors<br>
===========<br>
Davide Bertozzi<br>
Electrical Engineering Department University of Ferrara, Italy<br>
Email: dbertozzi@ing.unife.it<br>
<br>
Kees Goossens<br>
NXP Semiconductors Research, The Netherlands<br>
Computer Engineering Delft University of Technology, The Netherlands<br>
Email:kees.goossens@nxp.com<br>
<br>
Important Deadlines:<br>
================<br>
<br>
Submission deadline: July 6, 2008 <============== UPDATED<br>
Notification of Acceptance: November 1, 2008<br>
Final manuscript submission: January 1, 2009<br>
Target appearance date: March 2009 issue<br>
<br>
IET Computers & Digital Techniques is available through the IET Digital <br>
Library (</tt><tt><a href="http://ietdl.org/IET-CDT">http://ietdl.org/IET-CDT</a></tt><tt>) and IEEE Xplore platforms, and is <br>
indexed worldwide in all major databases including ISI, Inspec and EI <br>
Compendex.<br>
//<br>
--<br>
Prof. Davide Bertozzi<br>
Assistant Professor<br>
Engineering Department<br>
University of Ferrara<br>
Via Saragat, 1<br>
44100 Ferrara (Italy)<br>
Phone +39 0532974832<br>
Email: dbertozzi@ing.unife.it<br>
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