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<p>CALL FOR PAPERS IET Computers & Digital Techniques (Formerly IEE Proceedings Computers & Digital Techniques)<br>
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Special Issue on Networks On Chip<br>
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The most daunting challenge to future on-chip multiprocessor systems is to realise the enormous bandwidth capacities and stringent latency requirements when interconnecting a large number of processing cores in a power-efficient fashion. In a short time span, networks-on-chips have been recognised as the most important alternative for the design of modular and scalable communication architectures in the nanometre regime. This special issue intends to host relevant research contributions advancing knowledge in the field of on-chip networks. Submissions addressing design issues at all levels of abstraction are encouraged, from physical on-chip link design to data-link layer, from novel design-space exploration, ranging up to programming models and application software.<br>
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Topics of interest include but are not limited to:<br>
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Network architecture (topology, routing, arbitration)<br>
Power and energy issues in NoCs application-specific NoC design<br>
Timing, synchronous/asynchronous communication<br>
NoC case studies, application-specific NoC design<br>
NoC reliability issues<br>
O/S support for NoC<br>
Metrics and benchmarks for NoCs <br>
NoC Network interface issues <br>
Modelling, simulation, and synthesis of NoCs<br>
Network-on-chip design methodologies<br>
NoC Quality of Service<br>
NoC support for CMP / MPSoC<br>
NoC support for memory access<br>
NoCs for FPGAs and structured ASIC<br>
Programming models <br>
Mapping of applications onto NoCs<br>
Novel interconnect links / switches /routers<br>
Signaling and circuit design for NoC links<br>
Physical design of interconnect and NoC<br>
NoC design tools<br>
Debug & Test of NoC<br>
Floorplan aware NoC architecture optimisation<br>
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Submission details<br>
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Authors are encouraged to submit high-quality research contributions that will not require major revisions. Extensions of paper presented at the International Symposium on Networks-on-Chip, Newcastle Upon Tyne, United Kingdom, April 7-10, 2008 (<a href="http://async.org.uk/nocs2008">http://async.org.uk/nocs2008</a>), are especially encouraged, but work not presented at the symposium is also welcome. Please identify clearly the additional material from the original symposium paper in your submitted manuscript. A minimum of 30% new material is required, including deeper theory or extensions of experimental results. <br>
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Prospective authors should submit their manuscripts electronically via the IET CDT submission site: <a href="http://mc.manuscriptcentral.com/cdt">http://mc.manuscriptcentral.com/cdt</a>. Authors should clearly identify their papers as submissions for the Special Issue on Networks-on-Chip 2008 on their manuscript. All manuscripts are subject to the standard IET CDT review process. Instructions on how to submit a paper can be found at <a href="http://www.theiet.org/publications/journals/">http://www.theiet.org/publications/journals/</a> and authors can contact the journal's managing editor, Tony Donegan (tdonegan@theiet.org) , for further assistance.<br>
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Guest Editors<br>
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Davide Bertozzi<br>
Electrical Engineering DepartmUniversity of Ferrara, Italy <br>
Email: dbertozzi@ing.unife.it<br>
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Kees Goossens<br>
NXP Semiconductors Research, The Netherlands <br>
Computer Engineering Delft University of Technology, The Netherlands<br>
Email:kees.goossens@nxp.com<br>
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Important Deadlines:<br>
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Submission deadline: July 1, 2008<br>
Notification of Acceptance: November 1, 2008<br>
Final manuscript submission: January 1, 20<br>
Target appearance date: March 2009 issue<br>
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IET Computers & Digital Techniques is available through the IET Digital Library (<a href="http://ietdl.org/IET-CDT">http://ietdl.org/IET-CDT</a>) and IEEE Xplore platforms, and is indexed worldwide in all major databases including ISI, Inspec and EI Compendex. <br>
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<i>(See attached file: IET-CDT-CFP.pdf)</i><br>
--<br>
Prof. dr. Kees Goossens, Principal Research Scientist<br>
SOC Architectures and Infrastructure<br>
NXP Semiconductors / Corporate I&T / Research (formerly Philips Research)<br>
Room 2.047, High Tech Campus 37 (WY), 5656 AE Eindhoven, The Netherlands<br>
Phone: +31-40-27-29810 (NEW), Fax: +31-40-2746276<br>
Computer Engineering, Electrical Engineering Dept.<br>
Delft University of Technology, HB16.260, Mekelweg 4, 2628 CD Delft <br>
The Netherlands, Tel: +31-15-27-87354, Fax: +31-15-27-84898<br>
E-mail: kees.goossens@nxp.com<br>
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