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<tt>Technical event that may be of interest.</tt><br>
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<td>Synplify Pro and Synplify DSP Workshop at TU Delft, the
Netherlands</td>
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<th align="right" nowrap="nowrap" valign="baseline">Date: </th>
<td>Wed, 07 May 2008 01:00:00 -0700</td>
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<th align="right" nowrap="nowrap" valign="baseline">From: </th>
<td><a class="moz-txt-link-abbreviated" href="mailto:news@synplicity.com">news@synplicity.com</a></td>
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<p class="style13"><font color="#ffffff"
face="Arial, Helvetica, sans-serif"><strong><font size="2">Synplicity
Presents a FREE 2-Day Training Workshop</font> </strong></font></p>
<p class="style13"><font color="#ffffff"
face="Arial, Helvetica, sans-serif"><strong><font size="5">Synplify
Pro and Synplify DSP</font> </strong></font></p>
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<div align="center"><span class="style15"><font
face="Arial, Helvetica, sans-serif" size="2"><strong>at TU Delft, the
Netherlands, July 2-3, 2008</strong></font></span></div>
<div align="center">
<div align="left"><span class="style15"><font
face="Arial, Helvetica, sans-serif" size="2"><span
style="font-size: 10pt;">This course, arranged under the direction of
Synplicity’s worldwide University Programme, brings beginners from
basics towards using advanced features of Synplicity tools to create
DSP Applications.</span></font></span></div>
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<td colspan="3" valign="top" width="600"><span class="style11"><font
face="Arial, Helvetica, sans-serif" size="2">
<div align="center"><span class="style15"><font
face="Arial, Helvetica, sans-serif" size="2"><strong>Day 1: Technical
Tutorial – Synplify Pro (and introducing Synplify Premier)</strong></font></span></div>
<p><span style="font-size: 10pt; font-family: Arial;">Day 1
introduces the Synplify Pro tool. The course will familiarize students
with the FPGA design <span style=""> </span>flow and hands-on use of
features to actively create designs. The course then expands on these
concepts to focus on sophisticated design and analysis techniques,
debugging and high performance design. Knowledge acquired on day 1 of
the course is necessary for best understanding on day 2 – ESL Synthesis
Tutorial for DSP Algorithm Implementation.</span> </p>
<p><span class="style11"><font face="Arial, Helvetica, sans-serif"
size="2"><span class="style11"><font
face="Arial, Helvetica, sans-serif" size="2"><strong>Day 1 Agenda
(includes lectures and hands-on labs)</strong><br>
</font></span></font></span><span class="style11"><font
face="Arial, Helvetica, sans-serif" size="2"><span class="style11"><font
face="Arial, Helvetica, sans-serif" size="2">• Introduction<br>
• Getting Started <br>
• Timing Optimizations <br>
• Design Analysis and Debugging <br>
• Vendor Specific Topics <br>
• Formal Verification Flow with Synplify Pro <br>
• Synplify Premier Physical Synthesis </font></span></font></span><span
class="style11"><font face="Arial, Helvetica, sans-serif" size="2"></font></span></p>
</font></span></td>
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<div align="center"><span class="style15"><font
face="Arial, Helvetica, sans-serif" size="2"><strong>Day 2: Technical
Tutorial – ESL Synthesis Tutorial for DSP Algorithm Implementation</strong></font></span></div>
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<p><span class="style11"><font face="Arial, Helvetica, sans-serif"
size="2"><span style="font-size: 10pt; font-family: Arial;">Synplify
DSP implements DSP algorithms into FPGAs and ASICs, allowing the
transition from high-level models into silicon quickly and without
error. You will learn how Synplify DSP, its built-in DSP IP Library,
and The Mathworks Simulink environment can be combined to explore the
speed and area tradeoffs of different algorithms and architectures and
then to automatically generate RTL optimized for any FPGA or ASIC
target. The seminar will benefit engineers who are interested in:</span>
<br>
• Methods to rapidly create implementable algorithm models <br>
• Architectural exploration and analysis <br>
• Creating portable algorithmic IP that are re-usable across FPGA and
ASIC technologies </font></span></p>
<p><span class="style11"><font face="Arial, Helvetica, sans-serif"
size="2"><span class="style11"><font
face="Arial, Helvetica, sans-serif" size="2"><span class="style11"><font
face="Arial, Helvetica, sans-serif" size="2"><strong>Day 2 Agenda
(includes lectures and hands-on labs)<br>
</strong></font></span></font></span></font></span><span
class="style11"><font face="Arial, Helvetica, sans-serif" size="2">•
Introduction to Synplify DSP Flow<br>
• Architectural Exploration Overview<br>
• Signal Data Types<br>
• Vector Support<br>
• Multi-Rate Modeling<br>
• Architectural Synthesis <br>
• Micro-Architectural Optimizations<br>
• Retiming<br>
• Folding and Multi-Channelization<br>
• Advanced Features and IP Functions <br>
</font></span></p>
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src="cid:part2.08000205.00030009@ewi.tudelft.nl"></p>
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<p align="center"><font face="Arial, Helvetica, sans-serif"><strong>For
further information and registration, please visit: <font
color="#0000ff"><font face="Arial"><span
style="font-size: 10pt; font-family: Arial;"><font size="3"><a
href="http://lyris.mysynplicity.com/t/13880/406971/140/0/?u=aHR0cDovL3d3dy5zeW5wbGljaXR5LmNvbS9zeW5lX2RlbGZ0MDcwOC5odG1s&x=96f6fd48"></b></font><font color="red"><b>MailScanner has detected a possible fraud attempt from "lyris.mysynplicity.com" claiming to be</b></font> <font
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<p align="center"><font face="Arial, Helvetica, sans-serif" size="2">Synplicity,
Inc.<br>
600 West California Avenue<br>
Sunnyvale, CA 94086</font></p>
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<pre class="moz-signature" cols="72">--
=======================================================================
Georgi N. Gaydadjiev E-mail: <a class="moz-txt-link-abbreviated" href="mailto:georgi@ce.et.tudelft.nl">georgi@ce.et.tudelft.nl</a>
TU Delft (Delft University of Technology) Phone: +31 15 2786168
Faculty of Electrical Engineering, Fax: +31 15 2784898
Mathematics and Computer Science
Department of Microelectronics and Computer Engineering
Mekelweg 4, 2628 CD Delft, the Netherlands
<a class="moz-txt-link-freetext" href="http://ce.et.tudelft.nl/~georgi/">http://ce.et.tudelft.nl/~georgi/</a> IEEE E-mail: <a class="moz-txt-link-abbreviated" href="mailto:G.Gaydadjiev@ieee.org">G.Gaydadjiev@ieee.org</a>
=======================================================================
</pre>
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