[HiPEAC-announce] Call for Participation: Rapid Simulation and Performance Evaluation workshop :

[smail niar]

Rapid Simulation and Performance Evaluation: 

Methods and Tools 

(RAPIDO’09)

 <http://www2.lifl.fr/rapido09> http://www2.lifl.fr/rapido09

 

In conjunction with the 4th International Hipeac conference.

Paphos, Cyprus, January 25, 2009

 

Program and Call for Participation

Scope

The purpose of Rapido’09 is to bring researchers and practitioners from the
communities of embedded systems and general purpose systems together to
explore and discuss recent progress in the area of simulation and
performance evaluation techniques and tools. In the first part of the
workshop, in-depth technology challenges and state-of-the-art research
presentations will be given by 5 R&D actors from academia and industry. In
the second part, 7 selected research papers will be presented.

 

Organizers 

Smail Niar, University of Valenciennes and INRIA, France,
Smail.Niar at inria.fr

Rainer Leupers, Aachen University, Germany, leupers at iss.rwth-aachen.de

Olivier Temam, INRIA, France, Olivier.Temam at inria.fr

 

Advanced Program

INVITED SPEAKERS

09:00: SimFlex & ProtoFlex: Full-System Emulators/Simulators for Large-Scale
Multiprocessors

                Babak Falsafi, EPFL, Lausanne (Invited Speaker)

09:45: Performance Density Exploration of Heterogeneous Multicore
Architectures

Andrei Terechko, NXP, Eindhoven, the Netherlands (Invited Speaker)

10:30 Break

 

11:00 Architecture Exploration through Ultra-Fast Simulation

Nigel Topham, University of Edinburgh, UK (Invited Speaker)

11:45 Simulation and Validation: Challenges in Wireless Baseband Processing 

Norbert Wehn, TU Kaiserslautern, Germany (Invited Speaker)

12:30 Lunch

 

14:30 Know Before You Go: The Rise of System Level Simulation

Giovanni Beltrame, European Space Agency, the Netherlands (Invited Speaker)

 

 

RESEARCH PAPERS

 

15:15 Fast and Accurate Simulation Using the LLVM Compiler Framework

F. Brandner, A. Fellnhofer, A.S. Krall, and D.Riegler (Vienna University of
Technology, Austria)

15:35 Integration of Power Saving Techniques in the UNISIM Simulation
Framework through the 

                               Shadow Module Design Paradigm

D. Ludovici, G. Keramidas, G.N. Gaydadjiev and S. Kaxiras 

(Delft University of Technology, The Netherlands And University of Patras,
Greece)

 

15:55 Break

 

16:30 System Level Modelling for SpiNNaker CMP System 

M.M. Khan, E. Painkras, X. Jin, L.A. Plana, J.V. Woods and S.B. Furber 

(The University of Manchester, UK)

16:50 System Level Performance Simulation for Heterogeneous Multi-Processor
Architectures

M. Streubühr, C. Haubelt, and J. Teich (University of Erlangen-Nuremberg,
Germany)

17:10 Rapid Transactional Level Simulation for Multiprocessor Systems

I. Assayad and S. Yovine (Verimag, University of Grenoble, France)

 

 

17:30 Break

 

 

17:50 A DoE/RSM-based Strategy for an Efficient Design Space Exploration
Targeted to CMPs

                G. Palermo, C. Silvano, and  V. Zaccaria (Politecnico di
Milano, Italy)

18:10 Improving Cycle-level Modular Simulation by Vectorization

D. Parello, M. Bouache, and B. Goossens (University of Perpignan, France)

 

 

REGISTRATION 

The Rapido’09 workshop is affiliated with the 2009 Hipeac conference. To
register for the workshop, please visit:
<http://www.hipeac.net/conference/index.php?form=form1>
http://www.hipeac.net/conference/index.php?form=form1

 

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