[HiPEAC-announce] [Fwd: [Iccd09-list] ICCD 2009 Call for Paper]

[G N Gaydadjiev]

-------- Original Message --------
Subject: 	[Iccd09-list] ICCD 2009 Call for Paper
Date: 	Thu, 02 Apr 2009 16:05:28 -0500
From: 	Nam Sung Kim <nskim3 at wisc.edu>
To: 	iccd09-list at cae.wisc.edu



[Please accept our apologies if you receive multiple copies]

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CALL FOR PAPERS

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XXVII INTERNATIONAL CONFERENCE ON COMPUTER DESIGN 2009

Oct 4-7 2009, Resort at Squaw Creek, Lake Tahoe, California

_http://www.iccd-conference.org_

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Sponsored by (IEEE pending*): IEEE Computer Society, IEEE Circuits and 
Systems Society and IEEE Electron Devices Society

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IMPORTANT DATES

Submission deadline: May 8

Notification deadline: July 24

Final manuscript: August 24

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Disruptive Computer Design

The theme for ICCD 2009 is Disruptive Computer Design; submitted papers 
consistent with this theme are encouraged. Authors are invited to submit 
technical papers in accordance to the authors’ instructions describing 
original work in one of the following areas:

COMPUTER SYSTEMS: METHODS, IMPLEMENTATIONS AND APPLICATIONS

Advanced computer architecture for general and application-specific 
enhancement; System design methods for uni- and parallel processors; 
Design methods for homogeneous and heterogeneous multi-core processor 
systems and system-on-chip designs; IP and platform-based designs; HW/SW 
co-design; Modeling and performance analysis; Support for security, 
languages and operating systems; Smart Cards; Real-time Systems; 
Application-specific and embedded software optimization; Optimizing and 
parallelizing compiler support for multithreaded and multi-core designs; 
Memory system and Network system optimization.

PROCESSOR ARCHITECTURE

Microarchitecture design techniques for uni- and multi-core processors: 
instruction-level parallelism, pipelining, caching, branch prediction, 
multithreading, computer arithmetic; Techniques for low-power; secure, 
and reliable processor designs; Embedded, network, graphic, 
system-on-chip, application-specific and digital signal processor 
design; real-life design challenges: case studies, tradeoffs.

LOGIC AND CIRCUIT DESIGN

Circuits and design techniques for digital, memory, analog and 
mixed-signal systems; Circuits and design techniques for high 
performance and low power; Circuits and design techniques for robustness 
under process variability and radiation; Design techniques for emerging 
process technologies (MEMs, spintronics, nano, quantum); Asynchronous 
circuits; Signal processing and arithmetic circuits, and circuits for 
graphic processor design.

ELECTRONIC DESIGN AUTOMATION

High-level, logic and physical synthesis. Physical planning, design and 
early estimation for large circuits; Automatic analysis and optimization 
of timing, power and noise; Tools for multiple-clock domains, 
asynchronous and mixed timing methodologies; CAD support for FPGAs, 
ASSPs, structured ASICs, platform-based design and networks-on-chip; DfM 
and OPC methodologies; Tools, methodologies and design strate-gies for 
emerging technologies (MEMs, spintronics, nano, quantum).

VERIFICATION AND TEST

Functional, transaction-level, RTL, and gate-level modeling and 
verification of hardware designs; Simulation-based and formal techniques 
for functional design verification; Dynamic simulation, equivalence 
checking, formal verification, model and property checking, and theorem 
proving; high-level design validation; hardware emulation, modeling 
languages, assertion-based verification, coverage-analysis, 
constrained-random test generation; design error debug and diagnosis; 
Hardware/Software validation; Fault modeling; Fault simulation and ATPG; 
Fault tolerance; DFT and BIST; SoC verification.

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ORGANIZATION

Past Chair

Carl Pixley, Synopsys

General Chair

Kee Sup Kim, Intel

Peter-Michael Seidel, AMD

Technical Program Chairs

Georgi Gaydadjiev, TU Delft

Sofiene Tahar, Concordia University

Finance Chair

Stephen Wong, TU Delft

Publication Chairs

Suleyman Sair, North Carolina State University

Elaheh Bozorgzadeh, UC Irvine

Special Sessions Chair

Srikanath Venkataraman, Intel

Jim Sproch, Synopsis

Publicity Chairs

Nam Sung Kim, UW Madison

Ben Juurlink, TU Delft

Local Arrangement Chair

Hussain Al-Assad, UC Davis

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TRACK CHAIRS

Computer Systems Design and Applications Track

Greg Byrd, Carolina State University

Michael Gschwind, IBM

Processor Architecture Track

Jim Bondi, Texas Instruments

Eren Kursun, IBM

Logic and Circuit Design Track

Lars Svensson, Chalmers University of Technology, Sweden

Guy Even, Tel Aviv University

Electronic Design Automation Track

Jorg Henkel, University of Karlshrue

Farzan Fallah, Envis

Verification and Test Track

Sule Ozev, Duke University

Klaus Schneider, University of Kaiserslautern

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-- 
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Georgi N. Gaydadjiev                     Email: georgi at ce.et.tudelft.nl

TU Delft (Delft University of Technology)         Phone: +31 15 2786168

Department of Electrical Engineering,               Fax: +31 15 2784898
 
Mathematics and Computer Science  

Mekelweg 4, 2628 CD Delft, 

P.O. Box 5031

The Netherlands 

http://ce.et.tudelft.nl/~georgi/ 

IEEE Email: G.Gaydadjiev at ieee.org 

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