[HiPEAC-announce] Web seminar "Two recent works on power and thermal-aware load-balancing techniques for massive multi-core architectures", Tuesday 14, 12:00 (CET)

[Enric Morancho]

Dear colleague,

BSC-DAC-UPC invite you to attend online the following talk:

Title: "Hardware-based load balancing for massive multi-core 
architectures implementing power gating" and "Trading off higher 
execution latency for increased reliability in tile-based massive 
multi-core architectures"

Speaker: Enric Musoll (ConSentry Networks, Inc.)
Date: Tue 14, 12:00 (CET)
URL: http://www.ac.upc.edu/video/index,en.html

If you would like to ask questions to the speaker, please send an e-mail 
to seminar at hipeac.ac.upc.edu

Best regards,

Enric Morancho

"Hardware-based load balancing for massive multi-core architectures 
implementing
power gating" and "Trading off higher execution latency for increased 
reliabili
ty in tile-based massive multi-core architectures"
Enric Musoll (ConSentry Networks, Inc.)

Abstract

In this talk I will present two recent works on power and thermal-aware 
load-balancing techniques for massive multi-core architectures.

(a) Hardware-based load balancing for massive multi-core architectures 
implementing power gating
(To appear in the IEEE Transactions on Computer-Aided Design)

Abstract:

Many-core architectures provide a computation platform with high 
execution throughput, enabling them to efficiently execute workloads 
with a significant degree of thread-level parallelism. The burst-like 
nature of these workloads allows large power savings by power gating the 
idle cores. In addition, the load balancing of threads to cores also 
impacts the power and thermal behavior of the processor.

Processor implementations of many-core architectures may choose to group 
several cores into clusters sharing the area overhead, so that the whole 
cluster is power gated as opposed to the individual cores. However, the 
potential for power savings is reduced due to the coarser level of power 
gating.

In this work, several hardware-based, stateless load-balancing schemes 
are evaluated for these clustered homogeneous multi-core architectures 
in terms of their power and thermal behavior. All these methods can be 
unified into a parameterized technique that dynamically adjusts to 
obtain the desired goal (lower power, higher performance, lower hotspot 
temperature).

(b) Trading off higher execution latency for increased reliability in 
tile-based massive multi-core architectures
(Published at the 2009 IEEE International Symposium on Quality 
Electronics and Design)

Abstract:

Massive multi-core architectures provide a computation platform with 
high execution throughput, enabling the efficient execution of workloads 
with a significant degree of thread-level parallelism, like networking, 
DSP and e-commerce. The burst-like nature of these workloads render most 
of the cores idle most of the time. Therefore, there is a large 
potential for power savings by power gating these idle cores.
The ideal scenario from a power dissipation point of view is to execute 
the requests as fast as possible so that the cores can be power gated 
the longest. But due to the exponential dependency of (static) power on 
temperature, it may be the case that a cluster of spatially close cores 
consumes more than if these cores were farther apart from each other. 
The former case may certainly be best for performance (since the cores 
are closer to the neighbor's caches), but in the presence of spare cores 
in the die, it may be possible that by executing the requests in distant 
cores the overall throughput is still maintained and at the same time 
both power and hot spots are reduced, thus increasing the processor's 
reliability.

In this work, the power, performance and thermal behavior of a 
tile-based massive multi-core architecture is modeled and evaluated 
under different workload scenarios. Under a low ingress rate of requests 
or low inter-core communication traffic, both higher power savings and 
more uniformly chip wear are obtained by assigning requests to 
physically distant cores.

Bio

Enric Musoll graduated in computer science from the Polytechnic 
University of Catalonia at Barcelona (European Union) in 1993 and 
received the PhD in computer science from the same university in 1996 on 
the topic of low-power design. Since then, Enric has held industry 
positions in computer architecture, design and verification in National 
Semiconductor Corp. and in several start-up companies. Enric is 
currently co-founder of ConSentry Networks, where he has been 
instrumental in the design, tape-out and bring-up of the company's 
family of massive multi-core packet processors. His research interests 
include high-level synthesis techniques for low power and low-power 
high-performance computer architectures. Enric holds 20 granted patents 
and 23 publications in peer-reviewed international conferences and journals.