[HiPEAC-announce] MICRO-41 Call for Participation
Magklis, Grigorios
grigorios.magklis at intel.com
Sat Sep 6 09:02:32 CEST 2008
(Apologies if you receive multiple copies of this message)
======================================================================
CALL FOR PARTICIPATION
The 41st Annual IEEE/ACM International Symposium on Microarchitecture
(MICRO-41)
November 8-12, 2008
Lake Como, Italy
http://www.microarch.org/micro41
Co-sponsored by IEEE-CS TC-uARCH and ACM SIGMICRO
======================================================================
The 41st International Symposium on Microarchitecture is the premier
forum for presenting, discussing, and debating innovative
microarchitecture ideas and techniques for advanced computing and
communication systems. This symposium brings together researchers in
fields related to microarchitecture, compilers, chips, and systems for
technical exchange on traditional microarchitecture topics and
emerging research areas. The MICRO community has enjoyed a close
interaction between academic researchers and industrial designers and
we aim to continue this tradition at MICRO-41.
Important Dates
===============
Early registration closes: OCTOBER 6, 2008
Conference Program Summary
==========================
NOVEMBER 10 - 12
----------------
* Technical paper presentations (program available in the conference
website)
* KEYNOTES: David E. Shaw, Chief Scientist, D.E. Shaw Research and
Charles R. Moore, Senior Fellow, AMD
* ACTIVITIES: Lake boat tour and gala dinner at the Societa del Casino
in Como
NOVEMBER 8
----------
W2. Streaming Systems: From Web and Enterprise to Multicore -- Rodric
Rabbah, Xiaowei Shen, and Saman Amarasinghe
W3. New Frontiers in High-performance and Hardware-aware Computing
(HipHac) -- Rainer Buchty and Jan-Philipp Weiß
W4. 3rd Workshop on Dependable Architecture (WDA-3) -- Osman S. Unsal,
Oguz Ergin, and Yiannakis Sazeides
W5. Network on Chip Architectures (NoCArc) -- Maurizio Palesi and
Shashi Kumar
T2. On-Chip Communication Architectures: Busses, Networks-on-Chip and
Beyond -- Nikil Dutt, Luca Benini, and Sudeep Pasricha
T4. VLIW Compilation Environment and Multi-Processor Architecture of
Diopsis, the RISC+ floating-Point VLIW DSP System-On-Chip
Designed for High Quality Acoustic Applications -- Gert Goossens,
Pier Stanislao Paolucci and Piergiovanni Bazzana
T7. Performance Tools for Understanding the Behavior of Running
Programs on the Cell -- B.E Bilha Mendelson, Gadi Haber and
Thomas Chen
T9. Microprocessor Memory Array Circuits for Architects -- Shih-Lien
Lu, Dinesh Somasekhar and Steven Hsu
NOVEMBER 9
----------
W1. dasCMP: Workshop on Design, Architecture and Simulation of Chip
Multi-Processors -- Norman Jouppi, Rakesh Kumar, and Dean Tullsen
Tutorials (Nov 8 - 9):
T1. Programming Throughput-Oriented Architectures with Ct -- Anwar
Ghuloum, Gansha Wu and Xin Zhou
T3. Coherence and Memory Consistency Models -- Michel Dubois
T5. COTSon: Infrastructure for System-Level Simulation -- Theresa
Frawley, Vincent Lim, Ayose Falcon, Paolo Faraboschi and Daniel
Ortega
T6. Design Variability: Trends, Models, and Design Solutions -- Keith
Bowman, David Brooks, Gu-Yeon Wei and Chris Wilkerson
T8. Modeling, Verification and Mapping of Applications on WSN
Architectures -- Franco Fummi, Andrea Acquaviva, Davide Quaglia
and Giovanni Perbellini
T10. Changing Factors in Memory System Design -- Kenneth Wright and
Hillery Hunter
T11. CAD Solutions for System-Level Power Optimization -- Enrico Macii
and Massimo Poncino
Committees
==========
General Co-Chairs
-----------------
Antonio Gonzalez, Intel and UPC
Cristina Silvano, Politecnico di Milano
Program Co-Chairs
-----------------
Paolo Faraboschi, HP Labs
Steve Keckler, UT Austin
Workshops and Tutorials Co-Chairs
---------------------------------
Koen De Bosschere, Universiteit Gent
Donald Yeung, University of Maryland
Program Committee
-----------------
Ali-Reza Adl-Tabatabai, Intel
David Albonesi, Cornell
Saman Amarasinghe, MIT
Todd Austin, Univ. of Michigan
David Bernstein, IBM
Rajeev Balasubramonian, Univ. of Utah
David Christie, AMD
Tom Conte, Georgia Tech
Al Davis, HP Labs and Univ. of Utah
Jim Dehnert, Google
Giuseppe Desoli, STMicroelectronics
Evelyn Duesterwald, IBM
Joel Emer, Intel and MIT
Babak Falsafi, EPFL
Glenn Farrall, Infineon
Krisztian Flautner, ARM
Kim Hazelwood, Univ. of Virginia
Bruce Jacob, Univ. of Maryland
Richard Lethin, Reservoir Labs and Yale
Geoff Lowney, Intel
Bill Mangione-Smith, Intellectual Ventures
Srilatha Manne, AMD
Diana Marculescu, CMU
Onur Mutlu, Microsoft
Sanjay Patel, UIUC
Yale Patt, UT Austin
Li-Shiuan Peh, Princeton
Ravi Rajwar, Intel
Alex Ramirez, BSC and UPC
Karu Sankaralingam, Univ. of Wisconsin
Yannakis Sazeides, Univ. of Cyprus
Tim Sherwood, UC Santa Barbara
Guri Sohi, Univ. of Wisconsin
Olivier Temam, INRIA
Sudhakar Yalamanchili, Georgia Tech
Cliff Young, D.E. Shaw Research
Finance Chair
-------------
William Fornaciari, Politecnico di Milano
Publicity Chair
-------------
Grigorios Magklis, Intel
Web Chair
---------
Carlos Molina, Univ. Rovira i Virgili
Local Arrangements Co-Chairs
----------------------------
Gianluca Palermo, Politecnico di Milano
Giovanni Agosta, Politecnico di Milano
Publications Co-Chairs
----------------------
Matteo Monchiero, HP Labs
Carlo Galuzzi, TU Delft
Paper Submissions Chair
-----------------------
Mark Gebhart, UT Austin
Registration Chair
------------------
Jordi Tubella, UPC
Student Advocate
----------------
Pedro Marcuello, Intel
Steering Committee
------------------
Richard Belgard, Consultant (Chair)
Bob Colwell, Consultant
Tom Conte, Georgia Tech
Kemal Ebcioglu, Global Supercomputing
Wen-mei Hwu, UIUC
Scott Mahlke, University of Michigan
Bill Mangione-Smith, Intellectual Ventures
Yale Patt, UT Austin
Eric Rotenberg, NC State
John Shen, Nokia
Guri Sohi, University of Wisconsin
Mateo Valero, UPC
For more information visit the MICRO-41 web site at
http://www.microarch.org/micro41
-----------------------------------------------------------
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