[HiPEAC-announce] First Call For Papers: Workshop on HyperTransport Research and Applications (WHTRA)

Holger Fröning froening at uni-hd.de
Wed Sep 3 16:44:28 CEST 2008


========================================================================
                       Preliminary CALL FOR PAPERS
First International Workshop on HyperTransport Research and Applications
                                 (WHTRA)

                           February 12th, 2009
                           Heidelberg, Germany

                          http://whtra.uni-hd.de

========================================================================
The 1st International Workshop for Research on HyperTransport is an
international high quality forum for scientists, researches and
developers working in the area of HyperTransport. This includes not only
developments and research in HyperTransport itself, but also work which
is based on or enabled by HyperTransport. Beside regular contributions
we actively encourage papers about ongoing research, including new ideas
and learned lessons, ensuring up-to-date presentations during the
workshop.
The quality of the contributions is ensured by a peer review process.
Submissions will be accepted primarily for their impact on the
HyperTransport community and their innovative aspect. Accepted papers
will be published in the proceedings of the workshop. Because of the
international orientation of the workshop papers and presentations must
be composed in English. All submissions will be made electronically. For
more information please consult the workshop website
(http://whtra.uni-hd.de).

Papers are solicited in fields including (but not limited to) the
following:

o	HT caves, tunnels, switches and bridges
o	HT enabled applications
o	Embedded, high performance, “green” system architectures
o	On-chip networks
o	Network interfaces and interconnection networks
o	Fine grain computational problems and applications
o	Application specific processors and accelerators
o	Security processors
o	Reconfigurable architectures
o	High scalability systems

It is planned to let this workshop take place on a regular basis to
ensure a continuous knowledge exchange and to strengthen collaborations
within the community.

Background
==========
HyperTransport (HT) is an interconnection technology which is typically
used as system interconnect in modern computer systems, connecting the
CPUs among each other and with the I/O bridges. Primarily designed as
interconnect between high performance CPUs it provides an extremely low
latency, high bandwidth and excellent scalability. The definition of the
HTX connector allows the use of HT even for add-in cards. In opposition
to other peripheral interconnect technologies like PCI-Express no
protocol conversion or intermediate bridging is necessary. HT is a
direct connection between device and CPU with minimal latency. Another
advantage is the possibility of cache coherent devices.
Because of these properties HT is of high interest for high performance
I/O like networking and storage, but also for co-processing and
acceleration based on ASIC or FPGA technologies. In particular
acceleration sees a resurgence of interest today. One reason is the
possibility to reduce power consumption by the use of accelerators. In
the area of parallel computing the low latency communication allows for
fine grain communication schemes and is perfectly suited for scalable
systems. Summing up, HT technology offers key advantages and great
performance to any research aspect related to or based on interconnects.

Location and Event
==================
The Workshop for Research on HyperTransport will take place as an
accompanying event to the Second Symposium of the HyperTransport™ Center
of Excellence (HTCE) (http://htce2009.uni-hd.de) at the University of
Heidelberg, Germany. Both events are hosted by the Department of
Computer Engineering (http://www.ziti.uni-heidelberg.de). Exchange
between the participants of the Symposium and the Workshop is ensured by
the possibility of mutual participation.

Important Dates
===============
Paper Submission Deadline: November 28, 2008
Author Notification: TBD
Final Paper Due: TBD
Workshop: February 12, 2009

Committees
==========

Organizers
----------
Holger Fröning, Universität Heidelberg, Germany
Mondrian Nüssle, Universität Heidelberg, Germany
Pedro Javier García García, Universidad de Castilla-La Mancha, Spain

Program Committee
-----------------
Ulrich Brüning, Universität Heidelberg, Germany
José Duato, Universidad Politècnica de Valencia, Spain
Holger Fröning, Universität Heidelberg, Germany
Pedro Javier García García, Universidad de Castilla-La Mancha, Spain
Wolfgang Karl, Universität Karlsruhe, Germany
Mondrian Nüssle, Universität Heidelberg, Germany
Sudhakar Yalamanchili, Georgia Tech, U.S.
(to be completed)





-- 
Dr. Holger Fröning       (mailto:froening at uni-hd.de)
University of Heidelberg-Computer Architecture Group
URL:                       http://www.ziti.uni-hd.de
Tel.: +49.621.181.2718        Fax.: +49.621.181.2713
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