[HiPEAC-announce] CALL FOR PARTICIPATION:: DFT 2008

[cristiana bolchini]

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Apologies if you received multiple copies of this announcement.
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CALL FOR PARTICIPATION

IEEE DFT 2008
23rd International Symposium on Defect and Fault Tolerance in VLSI  
Systems

October 1-3, 2008, Cambridge/Boston, MA, USA
http://www.dfts.org
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IMPORTANT DATES

September 12th, 2008	Early Registration Deadline   (on-site  
registration is also possible)
October 1-3, 2008  		IEEE DFT 2008, Cambridge, MA, USA
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ABOUT DFT 2008
DFT is an annual Symposium, sponsored by the IEEE Computer Society,  
Fault-Tolerant Computing
Technical Committee, and Test Technology Technical Council. The event,  
this year the 23rd in a series,
provides an open forum for presentations in the field of defect and  
fault tolerance in VLSI systems
inclusive of emerging technologies. One of the unique features of this  
symposium is to combine
new academic research with state-of-the-art industrial data, necessary  
ingredients for significant
advances in this field. All aspects of design, manufacturing, test,  
reliability, and availability that are
affected by defects during manufacturing and by faults during system  
operation are of interest.

The technical program is available at
http://www.dfts.org/program.htm.
The program includes 12 regular sessions with 40 oral presentations,
1 poster paper sessions with 15 papers.
The sessions cover the following topics: Defect and Fault Tolerance,  
Dependability Analysis and Evaluation,
Design for Testability, Reliability and Fault Tolerance, Error  
Detection and Correction, Testing and Emerging Technologies.
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Keynote Speakers
The Evolving Role of Test ... it is now a “Value Add” Operation --  
Phil Nigh, IBM
Architectural Vulnerability Factor (or, does a soft error matter?) --  
Shubu Mukherjee, Intel

Invited Speakers
Error Detection and Tolerance for Scaled Electronic Technologies --  
Kartik Mohanram, Rice University
Targeting “Zero DPPM” – Can we ever get there? -- Nilanjan Mukherjee,  
Mentor Graphics
A Case Study of ATPG Delay Path Performance Based on Measured Power  
Rail Integrity -- Zahi Abuhamdeh, Transwitch
Computing at the Nanoscale -- John E. Savage, Brown University
Design for Test Challenges of High Performance/Low Power  
Microprocessors -- Kamran Zarrineh, AMD
Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits -- Konstantin K.  
Likharev, Stony Brook University

Panel: Zero Defects: How can we get there?
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ATTENDANCE AND REGISTRATION :  http://www.dfts.org/registration.html

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GENERAL CO-CHAIRS
Cristiana Bolchini, Politecnico di Milano, Italy
Yong-Bin Kim, Northeastern University, USA

PROGRAM CO-CHAIRS
Dimitris Gizopoulos, University of Piraeus, Greece
Mohammad Tehranipoor, University of Connecticut, USA
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