[HiPEAC-announce] Call for Participation - NoCArc 2008 1st Int. Workshop on Network on Chip Architectures at MICRO-41

[Maurizio Palesi]

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      *** EARLY ONLINE REGISTRATION EXTENDED UNTIL OCTOBER 15TH ***

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                        Call for Participation: NoCArc 2008
       First International Workshop on Network on Chip Architectures
              http://www.diit.unict.it/users/mpalesi/nocarc/
                       To be held in conjunction with
  the 41st Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-41)
                             8th November, 2008
                              Lake Como, Italy
=========================================================================

General Information
-------------------
Single chip embedded systems are becoming increasingly complex and
heterogeneous. Such Systems-on-Chip (SoCs) require seamless
integration of numerous IP cores performing different functions and
operating at different clock frequencies. Network-on-Chip (NoC) is
generally viewed as the ultimate solution for the design of modular
and scalable communication architectures and provides inherent support
to the integration of heterogeneous cores through the standardization
of the network interfaces. This workshop is focused on issues related
to  design, analysis and testing of on-chip networks.

The goal of the workshop is to provide a forum for researchers to
present and discuss innovative ideas and solutions related to design
and implementation of multi-core systems on chip.

More details about the workshop are available at
http://www.diit.unict.it/users/mpalesi/nocarc/

Preliminary Program
-------------------

13.30-14.20  Opening Session

       * Welcome

       * Keynote talk by José Duato - UPV Valencia, Spain


14.20-15.00  Session I - Router Microarchitecture

       * Planar Adaptive Router Microarchitecture for Tree-Based
         Multicast Network-on-Chip.
         F. A. Samman, T. Hollstein and M. Glesner
         TU Darmstadt, Germany

       * DMesh: a Diagonally-Linked Mesh Network-on-Chip Architecture
         W.-H. Hu and N. Bagherzadeh
         University of California, Irvine, USA


15.30-16.30  Session II - Performance Evaluation

       * Application Specific Buffer Allocation for Wormhole
         Routing Networks-on-Chip
         L. Wang, Y. Cao, X. Li and X. Zhu
         EIS, Wuhan University, China

       * A Generic Traffic Model for On-Chip Interconnection Networks
         J. H. Bahn and N. Bagherzadeh
         Qualcomm Inc., USA and UC Irvine, USA

       * A System-C based Microarchitectural Exploration Framework for
         Latency, Power and Performance Trade-offs of On-Chip
         Interconnection Networks
         B. Talwar and B. Amrutur
         ECE, Indian Institute of Science, Bangalore, India


16.40-17.40  Session III - Prospective Architectural Proposals

       * Scalable CMOS-compatible photonic routing topologies for
         versatile networks on chip
         A. Scandurra and I. O'Connor
         STMicrelectronics, Italy and Lyon Institute of
         Nanotechnology, France

       * Move Logic Not Data
         A. Hemani and M. A. Shami
         Royal Institute of Technology, KTH, Sweden

       * Hierarchical Agent Architecture for Scalable NoC Design
         with Online Monitoring Services
         A. W. Yin, L. Guang, P. Liljeberg, P. Rantala, E. Nigussie,
         J. Isoaho and H. Tenhunen
         University of Turku, Finland


Workshop Organizers
-------------------
* Maurizio Palesi
   Dipartimento di Ingegneria Informatica e delle Telecomunicazioni
   University of Catania, Italy
   http://www.diit.unict.it/users/mpalesi

* Shashi Kumar
   Department of Electronics and Computer Engineering
   School of Engineering
   Jönköping University, Sweden
   http://hem.hj.se/~kush/