[HiPEAC-announce] MICRO-41 early registration ends TODAY!
Magklis, Grigorios
grigorios.magklis at intel.com
Mon Oct 6 15:02:23 CEST 2008
(Apologies if you receive multiple copies of this message)
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C A L L F O R P A R T I C I P A T I O N --- M I C R O ' 0 8
The 41st Annual IEEE/ACM International Symposium on Microarchitecture
(MICRO-41)
November 8-12, 2008
Lake Como, Italy
http://www.microarch.org/micro41
Co-sponsored by IEEE-CS TC-uARCH and ACM SIGMICRO
======================================================================
The 41st International Symposium on Microarchitecture is the premier
forum for presenting, discussing, and debating innovative
microarchitecture ideas and techniques for advanced computing and
communication systems. This symposium brings together researchers in
fields related to microarchitecture, compilers, chips, and systems for
technical exchange on traditional microarchitecture topics and
emerging research areas. The MICRO community has enjoyed a close
interaction between academic researchers and industrial designers and
we aim to continue this tradition at MICRO-41.
REGISTER AT: http://www.microarch.org/micro41/pages/registration.html
*** EARLY REGISTRATION DEADLINE: October 6, 2008 ***
PROGRAM AVAILABLE AT: http://www.microarch.org/micro41/pages/program.html
==========================
Conference Program Summary
==========================
NOVEMBER 8
Tutorial (all day) - On-Chip Communication Architectures: Busses,
Networks-on-Chip and Beyond
Nikil Dutt, Luca Benini, and Sudeep Pasricha
Workshop (morning) - Streaming Systems: From Web and Enterprise to
Multicore
Rodric Rabbah, Xiaowei Shen, and Saman Amarasinghe
Workshop (morning) - 3rd Workshop on Dependable Architecture (WDA-3)
Osman S. Unsal, Oguz Ergin, and Yiannakis Sazeides
Tutorial (morning) - VLIW Compilation Environment and Multi-Processor
Architecture of Diopsis, the RISC+ floating-Point VLIW DSP
System-On-Chip Designed for High Quality Acoustic Applications
Gert Goossens, Pier Stanislao Paolucci and Piergiovanni Bazzana
Workshop (afternoon) - New Frontiers in High-performance and
Hardware-aware Computing (HipHac)
Rainer Buchty and Jan-Philipp Weiß
Workshop (afternoon) - Network on Chip Architectures (NoCArc)
Maurizio Palesi and Shashi Kumar
Tutorial (afternoon) - Performance Tools for Understanding the
Behavior of Running Programs on the Cell
B.E Bilha Mendelson, Gadi Haber and Thomas Chen
Tutorial (afternoon) - Microprocessor Memory Array Circuits for
Architects
Shih-Lien Lu, Dinesh Somasekhar and Steven Hsu
NOVEMBER 9
Workshop (all day) - dasCMP: Workshop on Design, Architecture and
Simulation of Chip Multi-Processors
Norman Jouppi, Rakesh Kumar, and Dean Tullsen
Tutorial (all day) - Coherence and Memory Consistency Models
Michel Dubois
Tutorial (morning) - Programming Throughput-Oriented Architectures
with Ct
Anwar Ghuloum, Gansha Wu and Xin Zhou
Tutorial (morning) - Design Variability: Trends, Models, and Design
Solutions
Keith Bowman, David Brooks, Gu-Yeon Wei and Chris Wilkerson
Tutorial (morning) - CAD Solutions for System-Level Power Optimization
Enrico Macii and Massimo Poncino
Tutorial (afternoon) - COTSon: Infrastructure for System-Level
Simulation
Theresa Frawley, Vincent Lim, Ayose Falcon, Paolo Faraboschi and
Daniel Ortega
Tutorial (afternoon) - Modeling, Verification and Mapping of
Applications on WSN Architectures
Franco Fummi, Andrea Acquaviva, Davide Quaglia and Giovanni
Perbellini
Tutorial (afternoon) - Changing Factors in Memory System Design
Kenneth Wright and Hillery Hunter
NOVEMBER 10
8:30 - 10:00 Keynote 1
Microarchitecture in the System-level Integration Era
Charles R. Moore, Senior Fellow, AMD
10:00 - 10:30 Coffee break
10:30 - 12:00 Session 1P: Instruction-Level Parallelism
12:00 - 13:30 Lunch
13:30 - 15:00 Session 2P: Cache Coherence and Cache Modeling
15:00 - 15:30 Coffe break
15:30 - 17:00 Session 3P: Cache Architectures for Security and
Availability
17:00 - 18:00 Special Session: "EU-US Funded Research Opportunities
and Trends in Computing Systems"
21:00 - 23:00 Business Meeting
NOVEMBER 11
8:30 - 10:00 Keynote 2
Architectures and Algorithms for Millisecond-Scale
Molecular Dynamics Simulations of Proteins
David E. Shaw, D.E. Shaw Research and Columbia University
10:00 - 10:30 Coffee break
10:30 - 12:30 Session 4A: Reliability, Availability, Security
Session 4B: Embedded and Special Purpose Architectures
12:30 - 13:30 Lunch
13:30 - 15:00 Session 5A: Memory and Cache Architectures
Session 5B: Transactions and Runtime Systems
15:00 - 15:30 Coffe break
15:30 - 17:00 Session 6A: Modeling, Simulation and Verification
Session 6B: Multicore and Multithreading
17:30 - 22:00 Lake Como boat tour (depending on weather conditions)
followed by Gala Dinner at Societa del Casino in Como
NOVEMBER 12
8:30 - 10:30 Session 7A: Interconnects
Session 7B: Process Variation
10:30 - 11:00 Coffee break
11:00 - 12:30 Session 8P: Circuits and Microarchitectures
12:30 - 13:30 Closing Session and Awards
==========
Committees
==========
General Co-Chairs
-----------------
Antonio Gonzalez, Intel and UPC
Cristina Silvano, Politecnico di Milano
Program Co-Chairs
-----------------
Paolo Faraboschi, HP Labs
Steve Keckler, UT Austin
Workshops and Tutorials Co-Chairs
---------------------------------
Koen De Bosschere, Universiteit Gent
Donald Yeung, University of Maryland
Program Committee
-----------------
Ali-Reza Adl-Tabatabai, Intel
David Albonesi, Cornell
Saman Amarasinghe, MIT
Todd Austin, Univ. of Michigan
David Bernstein, IBM
Rajeev Balasubramonian, Univ. of Utah
David Christie, AMD
Tom Conte, Georgia Tech
Al Davis, HP Labs and Univ. of Utah
Jim Dehnert, Google
Giuseppe Desoli, STMicroelectronics
Evelyn Duesterwald, IBM
Joel Emer, Intel and MIT
Babak Falsafi, EPFL
Glenn Farrall, Infineon
Krisztian Flautner, ARM
Kim Hazelwood, Univ. of Virginia
Bruce Jacob, Univ. of Maryland
Richard Lethin, Reservoir Labs and Yale
Geoff Lowney, Intel
Bill Mangione-Smith, Intellectual Ventures
Srilatha Manne, AMD
Diana Marculescu, CMU
Onur Mutlu, Microsoft
Sanjay Patel, UIUC
Yale Patt, UT Austin
Li-Shiuan Peh, Princeton
Ravi Rajwar, Intel
Alex Ramirez, BSC and UPC
Karu Sankaralingam, Univ. of Wisconsin
Yannakis Sazeides, Univ. of Cyprus
Tim Sherwood, UC Santa Barbara
Guri Sohi, Univ. of Wisconsin
Olivier Temam, INRIA
Sudhakar Yalamanchili, Georgia Tech
Cliff Young, D.E. Shaw Research
Finance Chair
-------------
William Fornaciari, Politecnico di Milano
Publicity Chair
-------------
Grigorios Magklis, Intel
Web Chair
---------
Carlos Molina, Univ. Rovira i Virgili
Local Arrangements Co-Chairs
----------------------------
Gianluca Palermo, Politecnico di Milano
Giovanni Agosta, Politecnico di Milano
Publications Co-Chairs
----------------------
Matteo Monchiero, HP Labs
Carlo Galuzzi, TU Delft
Paper Submissions Chair
-----------------------
Mark Gebhart, UT Austin
Registration Chair
------------------
Jordi Tubella, UPC
Student Advocate
----------------
Pedro Marcuello, Intel
Steering Committee
------------------
Richard Belgard, Consultant (Chair)
Bob Colwell, Consultant
Tom Conte, Georgia Tech
Kemal Ebcioglu, Global Supercomputing
Wen-mei Hwu, UIUC
Scott Mahlke, University of Michigan
Bill Mangione-Smith, Intellectual Ventures
Yale Patt, UT Austin
Eric Rotenberg, NC State
John Shen, Nokia
Guri Sohi, University of Wisconsin
Mateo Valero, UPC
-----------------------------------------------------------
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