[HiPEAC-announce] Call for Participation: Workshop on New Frontiers in High-performance and Hardware-aware Computing (HipHaC'08) at MICRO-41

[Rainer Buchty]

Preliminary program is now available. Early registration ends October 6.

All Information also accessible through http://www.hiphac.org/

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                    Call for Participation: HipHaC'08
                     First International Workshop on 
      New Frontiers in High-performance and Hardware-aware Computing
                     To be held in conjunction with
  the 41st Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-41)
                             November 8, 2008
                             Lake Como, Italy
=========================================================================

Heterogeneity and reconfigurability in computer systems are growing. Multi-
and manycore-based systems are complemented by coprocessors, accelerators,
and reconfigurable units providing huge computational power. However,
applications of scientific interest (e.g. in high-performance computing and
numerical simulation) are not yet ready to exploit the available high
computing potential. Different programming models, non-adjusted interfaces,
and bandwidth bottlenecks complicate holistic programming approaches for
heterogeneous architectures. In modern microprocessors, hierarchical memory
layouts and complex logics obscure predictability of memory transfers or
performance estimations.

The HipHaC workshop aims at combining new aspects of parallel, hetero-
geneous, and reconfigurable microprocessor technologies with concepts of
high-performance computing and, particularly, numerical solution methods.
Compute- and memory-intensive applications can only benefit from the full
hardware potential if all features on all levels are taken into account in a
holistic approach.

The workshop is a half day session and will feature an invited talk from
leading researchers in the field, as well as presentations selected
from the submissions.


Preliminary Workshop Program
----------------------------

13:30-14:40  Opening Session

 13:30	Welcome, Introduction & Overview

 13:40	Invited Talk
	Vincent Heuveline (Karlsruhe Institute of Technology, Germany)


14:40-15:00  Session I: Architecture

 14:40	OROCHI: A Multiple Instruction Set SMT Processor
	T. Nakada (Nara Institute of Science and Technology, Japan)


15:30-16:50  Session II: Stream Computing

 15:30	Experiences with Numerical Codes on the Cell Broadband Engine Architecture
	M. Stürmer, D. Ritter, H. Kostler, U. Rüde (Univ. Erlangen-Nürnberg, Germany)
	
 15:50	A Realtime Ray Casting System for Voxel Streams on the Cell Broadband Engine
	V. Fuetterling, C. Lojewski (Fraunhofer ITWM, Germany)

 16:10	Comparison of High-Speed Ray Casting on GPU using CUDA and OpenGL
	A. Weinlich, B. Keck, J. Hornegger (Univ. Erlangen-Nürnberg, Germany)

 16:30	RapidMind Stream Processing on the PlayStation 3 for a 3D Chorin-based
	Navier-Stokes Solver
	V. Heuveline, D. Lukarski, J.-P. Weiß (Karlsruhe Institute of Technology, Germany)


17:00-18:00  Session III: Temporal Locality

 17:00	Optimising Component Composition using Indexed Dependence Metadata
	L.W. Howes, A. Lokhmotov, P.H.J. Kelly, A.J. Field (Imperial College London, UK)

 17:20	Accelerating Stencil-Based Computation by Increased Temporal Locality on
	Modern Multi- and Many-Core Architectures
	M. Christen, O. Schenk, P. Messmer, E. Neufeld, H. Burkhart (Univ. Basel, Switzerland)

 17:40	Fast Cache-Miss Estimation of Loop Nests using Independent Cluster Sampling
	Kamal Sharma, Sanjeev Aggarwal, Mainak Chaudhuri, Sumit Ganguly (Indian Institute of Technology Kanput)


18:00 Closing 


Organizers
----------
Rainer Buchty, Karlsruhe Institute of Technology, Germany
Jan-Philipp Weiß, Karlsruhe Institute of Technology, Germany