[HiPEAC-announce] CFPs: 3rd International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC'09)

[José Flich]

(apologies for multiples copies of this CFPs)

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                          CALL FOR PAPERS

                         Third Workshop on
  Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC)
          (http://www.disca.upv.es/jflich/wina/wina09.html)

                     Held in conjunction with
     the 4th International Conference on High Performance Embedded
Architectures and Compilers (HiPEAC) (http://www.hipeac.net/conference)
             in Paphos, CYPRUS, January 25-28, 2009

Organizers:
- Tor Skeie, Simula Research Labs, Norway (General Chair)
- Davide Bertozzi, University of Ferrara, Italy (Program Co-Chair)
- José Flich, Techn. University of Valencia, Spain (Program Co-Chair)
- José Duato, Techn. University of Valencia, Spain (Steering Committee)
- Manolis Katevenis, FORTH-ICS, Greece (Steering Committee)

Solutions for communication between components within embedded and
parallel systems is undergoing rapid development. The move to
multi-core chips raises the need for scalable and power-efficient
interconnect fabrics able to realize large bandwidth capacities and
stringent latency requirements while meeting the constrains of
nanoscale physics. At the other end of the scale, parallel
supercomputers with tens of thousands of processors demand new and
scalable solutions to interconnections of its components.

This workshop concerns the architecture of interconnection switches
or routers, and networks of switches or routers, whether on-chip or
multi-chip. Topics of interest, within the context of interconnection
networks, include but are not limited to:

    * Networks-on-Chip (NoC)
    * Multi-Chip Interconn. Networks, including Cluster Interconnects
    * "Commodity Switches" as general-purpose building blocks
    * Switching, buffering, and routing architectures
    * Flow control and congestion management in switching fabrics
    * Virtualization
    * Topology exploration
    * Timing, synchronous/asynchronous communication
    * Reliability, availability, fault tolerance
    * Area/power versus functionality/QoS support in NoC architectures
    * Design space exploration
    * NoC physical link design

The goal of the workshop is to provide a forum for presenting and
discussing mostly work in progress, or ideas for future research in
response to future trends. The workshop intends to include a couple of
presentations by experts in the field about the current
state-of-the-art and where we need to go, and intends to encourage
discussions among the participants. It does not matter if the views
and opinions expressed are "wild and crazy", as long as they have
been carefully thought out and they are intuitively sound and
implementable. This is the third year of the workshop. In its previous
editions the workshop exhibited a competent audience and interesting
discussions arose from the different presentations of authors.

Important dates

Submission deadline: November 21st, 2008
Notification to authors: December 26th, 2008

Program committee:

- Federico Angiolini - EPFL Lausanne (Switzerland)
- Luca Benini, University of Bologna, Italy
- Ulrich Bruening - University of Heidelberg (Germany)
- Marcello Coppola - STMicroelectronics (France)
- Ran Ginosar, Technion, Israel   
- Kees Goossens - NXP (Holland)
- Mark Hummel - AMD (USA)
- Janusz Kleban - Poznan University (Poland)
- Dimitris Lioupis - University of Patras (Greece)
- Olav Lysne - Simula Research Labs (Norway)
- Cyriel Minkenberg - IBM (Zurich)
- Robert Mullins - University of Cambridge (United Kingdom)
- Timothy Pinkston - University of Southern California (USA)
- Dionisios Pnevmatikatos - ICS-FORTH (Greece)
- José Luis Sánchez - University of Castilla-La Mancha (Spain)
- Li Shiuan Peh - Princeton University (USA)
- Hannu Tenhunen - Royal Institute of Technology (Sweden)
- Pascal Vivet - MINATEC (France)
- Sudhakar Yalamanchili - Georgia Institute of Technology (USA)

Submissions and acceptance will be in the form of extended abstracts
of length 3-5 pages. The submission procedure will be through the EDAS
web-page (http://www.disca.upv.es/jflich/wina/wina09.html). There will
be no Proceedings, but we will encourage authors to electronically share
their texts and slides with all participants.