[HiPEAC-announce] CFP: 6th HiPEAC Industrial Workshop on Compilers and Architectures [reminder]

[Sami Yehia]

Apologies if you receive multiple copies of this.


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               Call for Paper
        6th HiPEAC Industrial Workshop
            November 26th, 2008
  Thales Research & Technology Palaiseau, France

      Domain specific, real time and
     safety critical embedded systems
         in the multi-core era
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http://www.hipeac.net/industry_workshop6

The ubiquity of embedded electronics in all aspects of human life as  
well as
the emerging applications in automotive, aerospace and security industry
suggest multi-core architectures as a natural path to scalable  
performance.
Still, such applications have challenging requirements beyond those  
existing
in high performance computing and high volume embedded systems.

Beside the increasing need of performance, low power consumption, and  
the
challenges the industry is facing to effectively program parallel
architectures, such specific systems are usually subject to conflicting
requirements such as flexibility (or “genericity”) to compensate for low
volume production needs, and customizability to address each application
domain needs.

Furthermore, a lot of these systems, especially in the automotive and  
the
aerospace domains, are subject to hard real time and safety critical
requirements that reduce the efficiency and potential of current multi- 
cores
and high performance architectures.

The goal of this workshop is to bring together researchers from  
academia and
industry to investigate the challenges, techniques, tools and  
requirements
of multi-core architectures in embedded systems, especially in the
automotive, aerospace, and security industry.

The topics of interest include, but are not limited to:
* Processor customization and application specific architectures
* Parallel and multi-core systems for real time and safety critical  
systems
(including performance predictability, reliability constraints, …).
* Low power techniques for multi-cores
* Reconfigurable and adaptive architectures
* Heterogeneous multi-core architectures and virtualization techniques
* Compilers, tools and methods for embedded, high performance and
heterogeneous parallel architectures
* Mapping parallel applications to heterogeneous multi-cores
* Simulation tools, design space exploration and performance modeling of
multi-core and/or application specific architectures
* Benchmarks and performance metrics
* Iterative compilation techniques for embedded and high performance  
systems
* Domain/application specific accelerators

Important Dates
Submission deadline: October 15th, 2008
Notification of acceptance: November 1st, 2008
Workshop: November 26th, 2008

Submissions

Authors should submit their contributions electronically to Sami Yehia
(sami.yehia at thalesgroup.com). Submissions must include a 2-page extended
abstract describing the work that is going to be presented. An early  
email
with your intention to submit a paper would be greatly appreciated.  
Authors
should feel free to present work in progress as well as already  
published
material, and can include related documents with additional details on  
their
research work. Authors should commit to present their research at the
workshop in the case it gets selected. Abstract and other workshop  
material
will be made available online at http://www.hipeac.net/. The workshop  
will
not publish proceedings. While this workshop is organized by HiPEAC, the
host (Thales Research & Technology) is solely responsible for the  
selection
process.

Feel free to forward this call for papers in your institution.

Contact us
Sami Yehia, Thales Research & Technology, Embedded Systems Lab,
(sami.yehia at thalesgroup.com)


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