[HiPEAC-announce] SUBMISSION DEADLINE EXTENDED: 1st HiPeac Workshop on Design for Reliability (DFR'09)

[Theocharis Theocharides]

(We apologize if you receive multiple copies of this message.) 
DEADLINE EXTENSION: The deadline for submissions has been extended to
November 10, 2008, 11:59PM PST. An abstract must be deposited by the
original deadline, November 3, 2008, 11:59PM PST. 
RECENT NEWS: Selected papers will be considered for inclusion on a special
issue of the Transactions on HiPEAC, http://www.hipeac.net/journal.

Please feel free to contact us if you have any questions. 

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CALL FOR PAPERS FOR THE 1st Workshop on Design for Reliability (DFR'09)
held in conjunction with the 4th International Conference on High
Performance and 
Embedded Architectures and Compilers (HiPEAC'09)
http://www.hipeac.net/conference/
January 25-28, 2009 Paphos, CYPRUS

Important dates:
Abstract Deadline: November 3, 11:59PM PST 
Submission Deadline: November 10, 11:59PM PST (extended)
Notification of acceptance: December 8, 2008 
Camera-ready submission: December 19, 2008 
Workshop Date: Half Day, Sunday, January 25, 2009

Workshop Web site:
http://www.eng.ucy.ac.cy/theocharides/dfr09/index.htm

Motivation:
While technology is scaling well into the nanometer era, design of reliable,
dependable and verifiable systems emerges as one of the most prominent
design challenges. As device size and power supply voltage shrink, the rate
of intermittent and permanent faults rises significantly due to design
errors, device variability and manufacturing defects, as well as
environmental impact and aging of devices. Increased process variation also
shifts the traditional deterministic design methodology towards a more
stochastic and unorthodox design paradigm. Furthermore, these issues cause
further challenges in completing design verification and manufacturing test;
such effects manifest as inherent unreliability of the components,
redefining the design and test paradigm for next-generation computing
systems. Additionally, energy reduction and performance enhancement
techniques force designs to run near zero margins, and factors which cannot
be controlled such as soft errors, thermal impact and aging, result in an
increased occurrence of transient and hard faults in computing systems.

The goal of DFR'09 is to stimulate interest in an emerging and challenging
issue by bringing together researchers from various areas (design,
verification, test, architecture, fault-tolerance and reliability) to share
ideas and ferment future research in holistic approaches for reliable
next-generation computing systems.

Topics of interest include (but are not limited to):
* Dependable systems from unreliable components, lifelong reliability
* Fault-Tolerant micro-architectures and system architectures
* Testing and verification strategies for the future
* On-line (dynamic) testing and verification techniques
* Software-based methodologies for fault tolerance and testing
* System validation mechanisms
* Built-in self diagnosis, self-tuning and recovery schemes
* Self-adaptive systems
* System-level design and integration for reliability, verifiability and
dependability
* Error modelling, detection, correction, and tolerance for transient and
permanent errors
* Reliable on-chip communications
* Energy/reliability/performance tradeoffs
* Aggressive power saving mechanisms
* Compiler/architecture/OS methodologies and strategies for reliability

Submission guidelines:
Authors are invited to submit unpublished mature as well as preliminary /
on-going work. Submitted papers should be in the LNCS format (for manuscript
preparation guidelines visit http://www.springeronline.com/lncs)
and should not exceed 10 pages. Papers must be submitted in the PDF
(preferably) or postscript formats to the DFR'09 submission website, which
can be found at the workshop's website.. 
Selected papers will be considered for inclusion on a special issue of the
Transactions on HiPEAC, http://www.hipeac.net/journal. 
Paper and electronic proceedings with all accepted papers will be 
distributed at the workshop

Program Committee:
Jacob Abraham, University of Texas at Austin,USA
Todd Austin, University of Michigan, USA 
Luca Benini, University of Bologna, ITALY 
David Bernstein, IBM, Haifa, ISRAEL 
Davide Bertozzi, University of Ferrara, ITALY 
Veerle Desmet, Ghent University, BELGIUM 
Oguz Ergin, TOBB University of Economics and Technology, TURKEY 
Babak Falsafi, Ecole Polytechnique Fédérale de Lausanne, SWITZERLAND 
Said Hamdioui, Delft University of Technology, NETHERLANDS 
Paolo Ienne, Ecole Polytechnique Fédérale de Lausanne, SWITZERLAND 
Mary Jane Irwin, Pennsylvania State University, USA 
Peter Marwedel, Technische Universität Dortmund, GERMANY 
Maria K. Michael, University of Cyprus, CYPRUS 
Shubu Mukherjee, Intel Corporation, USA 
Alex Orailoglu, University of California, San Diego, USA 
Emre Ozer, ARM, UK 
Theocharis Theocharides, University of Cyprus, CYPRUS

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Best Regards,

The Workshop Organizers

Alex Orailoglu, University of California, San Diego, USA
alex[at]cs[dot]ucsd[dot]edu

Theocharis Theocharides, University of Cyprus, CYPRUS
ttheocharides[at]ucy[dot]ac[dot]cy

Maria K. Michael, University of Cyprus, CYPRUS 
mmichael[at]ucy[dot]ac[dot]cy

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