[HiPEAC-announce] Last CFP, ICCD 2008, Lake Tahoe, CA

[Ben Juurlink]

** EXTENDED SUBMISSION DEADLINES!**

[Please accept our apologies if you receive multiple copies]

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CALL FOR PAPERS
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XXVI  INTERNATIONAL CONFERENCE ON COMPUTER DESIGN 2008

Oct 12-15 2008, Resort at Squaw Creek, Lake Tahoe, California
http://www.iccd-conference.org

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Sponsored by IEEE: IEEE Computer Society, IEEE Circuits
and Systems Society and IEEE Electron Devices Society

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IMPORTANT DATES:
**EXTENDED SUBMISSION DEADLINES**

Abstract Submission Deadline: (Firm)
Friday  May 16,  2008  11:59pm HST Hawaii Time(GMT-10 hours)

Full Manuscript Submission Deadline: (Firm)
Thursday  May 22,  2008  11:59pm HST Hawaii Time(GMT-10 hours)

Notification: July 18

Final Manuscript: August 22:

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GREEN COMPUTING

The theme for ICCD 2008 is Green Computing; submitted papers consistent
with this theme are encouraged. Authors are invited to submit technical
papers in accordance to the authors’ instructions describing original work
in one of the following areas:

COMPUTER SYSTEMS: METHODS, IMPLEMENTATIONS AND APPLICATIONS
Advanced computer architecture for general and application-specific
enhancement; System design methods for uni- and parallel processors; Design
methods for homogeneous and heterogeneous multi-core processor systems and
system-on-chip designs; IP and platform-based designs; HW/SW co-design;
Modeling and performance analysis; Support for security, languages and
operating systems; Smart Cards; Real-time Systems; Application-specific and
embedded software optimization; Optimizing and parallelizing compiler
support for multithreaded and multi-core designs; Memory system and Network
system optimization.

PROCESSOR ARCHITECTURE
Microarchitecture design techniques for uni- and multi-core processors:
instruction-level parallelism, pipelining, caching, branch prediction,
multithreading, computer arithmetic; Techniques for low-power; secure, and
reliable processor designs; Embedded, network, graphic, system-on-chip,
application-specific and digital signal processor design; real-life design
challenges: case studies, tradeoffs.

LOGIC AND CIRCUIT DESIGN
Circuits and design techniques for digital, memory, analog and mixed-signal
systems; Circuits and design techniques for high performance and low power;
Circuits and design techniques for robustness under process variability and
radiation; Design techniques for emerging process technologies (MEMs,
spintronics, nano, quantum); Asynchronous circuits; Signal processing and
arithmetic circuits, and circuits for graphic processor design.

ELECTRONIC DESIGN AUTOMATION
High-level, logic and physical synthesis: Physical planning, design and
early estimation for large circuits; Automatic analysis and optimization of
timing, power and noise; Tools for multiple-clock domains, asynchronous and
mixed timing methodologies; CAD support for FPGAs, ASSPs, structured ASICs,
platform-based design and networks-on chip; DfM and OPC methodologies;
Tools, methodologies and design strategies for emerging technologies (MEMs,
spintronics, nano, quantum); Functional, transaction-level, RTL, and
gate-level modeling and verification of hardware designs; Simulation-based
and formal techniques for functional design verification; Dynamic
simulation, equivalence checking, formal verification, model and property
checking, and theorem proving; high-level design validation; hardware
emulation, modeling languages, assertion-based verification,
coverage-analysis, constrained-random test generation; design error debug
and diagnosis; Hardware/Software validation; Fault modeling; Fault
simulation and ATPG; Fault tolerance; DFT and BIST; SoC verification.
Proposals for embedded tutorials and panel discussions are also solicited,
and should be sent to: Sule Ozev, sule at ee.duke.edu

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ORGANIZATION
Past Chair
Kevin Rudd, Intel

General Chair
Carl Pixley, Synopsys

Technical Program Chairs
Peter-Michael Seidel, AMD
Georgi Gaydadjiev, TU Delft

Finance Chair
Kee Sup Kim, Intel Corporation

Publication Chairs
Greg Byrd and Suleyman Sair, North Carolina State University

Special Sessions Chair
Sule Ozev, Duke University

Publicity Chairs
Eren Kursun, IBM Research
Ben Juurlink, TU Delft

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TRACK CHAIRS
Computer Systems Design and Applications Track
Valentina Salapura, IBM TJ Watson
Fadi Kurdahi, University of California at Irvine

Processor Architecture Track
John Glossner, Sandbridge Technologies
Jarmo Takala, Tampere University of Technology

Logic and Circuit Design Track
Voijn Oklobdzjia, University of Texas at Dallas
Lars Svensson, Chalmers University of Technology, Sweden

Electronic Design Automation Track
Ryan Kastner, University of California at Santa Barbara
Farzan Fallah, Fujitsu Labs

Verification and Test Track
Patrick Girard, LIRMM
Sofiene Tahar, Concordia University
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