[HiPEAC-announce] [Fwd: Synplify Pro and Synplify DSP Workshop at TU Delft, the Netherlands]

[G.N.Gaydadjiev]

Technical event that may be of interest.

-------- Original Message --------
Subject: 	Synplify Pro and Synplify DSP Workshop at TU Delft, the 
Netherlands
Date: 	Wed, 07 May 2008 01:00:00 -0700
From: 	news at synplicity.com
To: 	



*Synplicity Presents a FREE 2-Day Training Workshop *

*Synplify Pro and Synplify DSP *

*at TU Delft, the Netherlands, July 2-3, 2008*
This course, arranged under the direction of Synplicity's worldwide 
University Programme, brings beginners from basics towards using 
advanced features of Synplicity tools to create DSP Applications.
*Day 1: Technical Tutorial - Synplify Pro (and introducing Synplify 
Premier)*

Day 1 introduces the Synplify Pro tool. The course will familiarize 
students with the FPGA design  flow and hands-on use of features to 
actively create designs. The course then expands on these concepts to 
focus on sophisticated design and analysis techniques, debugging and 
high performance design. Knowledge acquired on day 1 of the course is 
necessary for best understanding on day 2 - ESL Synthesis Tutorial for 
DSP Algorithm Implementation.

*Day 1 Agenda (includes lectures and hands-on labs)*
. Introduction
. Getting Started
. Timing Optimizations
. Design Analysis and Debugging
. Vendor Specific Topics
. Formal Verification Flow with Synplify Pro
. Synplify Premier Physical Synthesis

*Day 2: Technical Tutorial - ESL Synthesis Tutorial for DSP Algorithm 
Implementation*

Synplify DSP implements DSP algorithms into FPGAs and ASICs, allowing 
the transition from high-level models into silicon quickly and without 
error. You will learn how Synplify DSP, its built-in DSP IP Library, and 
The Mathworks Simulink environment can be combined to explore the speed 
and area tradeoffs of different algorithms and architectures and then to 
automatically generate RTL optimized for any FPGA or ASIC target. The 
seminar will benefit engineers who are interested in:
. Methods to rapidly create implementable algorithm models
. Architectural exploration and analysis
. Creating portable algorithmic IP that are re-usable across FPGA and 
ASIC technologies

*Day 2 Agenda (includes lectures and hands-on labs)
*. Introduction to Synplify DSP Flow
. Architectural Exploration Overview
. Signal Data Types
. Vector Support
. Multi-Rate Modeling
. Architectural Synthesis
. Micro-Architectural Optimizations
. Retiming
. Folding and Multi-Channelization
. Advanced Features and IP Functions

	

*For further information and registration, please visit: *MailScanner 
has detected a possible fraud attempt from "lyris.mysynplicity.com" 
claiming to be* http://www.synplicity.com/syne_delft0708.html 
<http://lyris.mysynplicity.com/t/13880/406971/140/0/?u=aHR0cDovL3d3dy5zeW5wbGljaXR5LmNvbS9zeW5lX2RlbGZ0MDcwOC5odG1s&x=96f6fd48>*

	

 

Synplicity, Inc.
600 West California Avenue
Sunnyvale, CA 94086

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-- 
======================================================================= 

Georgi N. Gaydadjiev                    E-mail: georgi at ce.et.tudelft.nl 

TU Delft (Delft University of Technology)         Phone: +31 15 2786168 

Faculty of Electrical Engineering,                  Fax: +31 15 2784898 
 
Mathematics and Computer Science 

Department of Microelectronics and Computer Engineering

Mekelweg 4, 2628 CD Delft, the Netherlands 

http://ce.et.tudelft.nl/~georgi/     IEEE E-mail: G.Gaydadjiev at ieee.org 

======================================================================= 

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