[HiPEAC-announce] CFP CMP-MSI 2008 (ISCA-35 Workshop)

[Yiannakis Sazeides (Yanos)]

CALL FOR PAPERS

--------------------------------------------------------------------------------

CMP-MSI: 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects

In conjunction with the 35th International Symposium on Computer 
Architecture (ISCA-35)

Sunday, June 22nd, 2008
Beijing, China

--------------------------------------------------------------------------------


Scope:
------

Chip multiprocessors (CMPs) are emerging as the architecture of choice for 
future high performance processors. CMPs integrate several 
high-performance processing cores onto the same chip. A high performance 
interconnect and memory system are necessary to satisfy the data supply 
needs of all these cores especially given the ever increasing speed gap 
between processors and main memory systems. At the same time, power, 
temperature, complexity, and reliability are additional constraints that 
must be met by any design.
The fact that now these components will be tightly integrated onto the 
same die presents opportunities and challenges that are very different 
than those that existed in previous multi-processor systems. This workshop 
aims to become a forum for academia and industry to discuss and present 
ideas and recent developments in the design and evaluation of on-chip 
multiprocessor memory systems and interconnects.


Call for Papers:
----------------

Two kinds of papers are invited:

Technical papers (at least 6 pages) for relatively mature ideas.
Position papers (3 pages maximum) on directions for research and 
development.

Please submit an electronic copy of your paper (in PDF) in two column 
format with at least 10pt font. For submission instructions and 
workshop related announcements check www.cs.utah.edu/cmpmsi08/

The selected papers will be made available online. However, publication in 
CMP-MSI does not preclude later publication at regular conferences or 
journals. Some papers may be nominated for inclusion in a "Best of ISCA 
2008 Workshops" special issue journal publication.

Topics of interest include:
---------------------------

Memory system design and optimizations
Interconnect design and optimizations
Policies for non-uniform cache access (NUCA) and shared/private caching
3D stacked cache hierarchies
Improvements to cache hierarchy and interconnect power, temperature, 
reliability, security, and complexity
Coherence optimizations
Memory system support for alternative execution models such as 
transactional memory
Memory and interconnect designs for heterogeneous CMP architectures where 
some of the computation cores are specialized (e.g., GPUs)
Support for software optimizations and or enhanced functionality (e.g., 
debugging, tracing, checkpointing)
Early reports on system prototypes

Important Dates:
----------------

Paper Due: April 18, 2008 (11.59PM, PDT)
Notification: May 19, 2008
Final Paper Due: May 26, 2008

Organizers:
-----------

Rajeev Balasubramonian , University of Utah
Andreas Moshovos , University of Toronto
Yiannakis Sazeides , University of Cyprus

Program Committee:
------------------

Tor Aamodt, Univ. of British Columbia, Canada
Dave Albonesi, Cornell University, USA
Matt Blumrich, IBM, USA
David Brooks, Harvard University, USA
Srihari Makineni, Intel Corp., USA
Avi Mendelson, Intel Corp., Israel
Pierre Michaud, IRISA/INRIA, France
Li-Shiuan Peh, Princeton University, USA
Ronny Ronen, Intel Corp., Israel
Karu Sankaralingam, University of Wisconsin, USA
Yiannis Schoinas, Intel Corp., USA
Viji Srinivasan, IBM, USA
Thomas Wenisch, University of Michigan, USA