[HiPEAC-announce] CFP: NoCArch 2008 - First International Workshop on Network on Chip Architectures

Maurizio Palesi mpalesi at diit.unict.it
Mon Jul 21 14:44:15 CEST 2008


[Our apologies if you receive multiple copies of this CFP]

=========================================================================
                        Call for Papers: NoCArc 2008
       First International Workshop on Network on Chip Architectures
                       To be held in conjunction with
  the 41st Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-41)
                             8th November, 2008
                              Lake Como, Italy
=========================================================================

General Information
-------------------
Single chip embedded systems are becoming increasingly complex and
heterogeneous. Such Systems-on-Chip (SoCs) require seamless
integration of numerous IP cores performing different functions and
operating at different clock frequencies. Network-on-Chip (NoC) is
generally viewed as the ultimate solution for the design of modular
and scalable communication architectures and provides inherent support
to the integration of heterogeneous cores through the standardization
of the network interfaces. This workshop is focused on issues related
to  design, analysis and testing of on-chip networks.

Areas of Interest
-----------------
The topics of specific interest for the workshop include, but are not
limited to:

*  Architectures and Topologies for NoCs and MPSoCs
*  Routing algorithms and Router Micro-architectures
*  Fault tolerance, reliability and testing issues
*  Dynamic on-chip network reconfiguration
*  Modeling and evaluation of on-chip networks
*  Design space exploration and tradeoff analysis
*  On-chip interconnection network simulators and emulators
*  Industrial case studies of SoC designs using the NoC paradigm

The goal of the workshop is to provide a forum for researchers to
present and discuss innovative ideas and solutions related to design
and implementation of multi-core systems on chip.  Besides regular
papers, papers describing "work in progress" or incomplete but sound
new innovative ideas related to the workshop theme are also
encouraged.

Submission Guidelines
---------------------

The authors are invited to submit unpublished work related to
workshopss s theme. Both research and application-oriented papers are
welcome. All papers should be submitted electronically via the
workshop web-page at:

http://www.diit.unict.it/users/mpalesi/nocarc/.

Papers must be in PDF format and should include title, authors and
affiliation, e-mail address of the contact author. Papers should be
formatted in accordance with the templates published in the workshop
webpage (standard double-column IEEE in A4 format). Submissions must
be limited to 6 pages. If the authors wish a blind review to be
performed, then the author's name and affiliation should be omitted in
the submitted paper. In case of any questions please contact the
workshop organizers.

Important Dates
---------------
Submission deadline       24th August, 2008
Author notification       1st October, 2008
Camera-ready version due 10th October, 2008
NoCArc Workshop          8th November, 2008

Workshop Organizers
-------------------
* Maurizio Palesi
   Dipartimento di Ingegneria Informatica e delle Telecomunicazioni
   University of Catania, Italy
   http://www.diit.unict.it/users/mpalesi

* Shashi Kumar
   Department of Electronics and Computer Engineering
   School of Engineering
   Jönköping University, Sweden
   http://hem.hj.se/~kush/

Program Committee
-----------------
* Federico Angiolini, iNoCs, Switzerland
* Davide Bertozzi, University of Ferrara, Italy
* Giorgos Dimitrakopoulos, FORTH, Greece
* José Flich Cardo, Universidad Politécnica de Valencia, Spain
* Ahmed Hemani, Royal Institute of Technology, Sweden
* Anshul Kumar, Indian Institute of Technology, India
* Marcello Lajolo, NEC Laboratories America, NJ, USA
* Zhonghai Lu, Royal Institute of Technology, Sweden
* Srinivasan Murali, EPFL, Switzerland and Stanford University, USA
* Juan Manuel Orduña Huertas, Universidad de Valencia, Spain
* Davide Patti, University of Catania, Italy
* Partha P. Pande, Washington State University, USA
* Timothy M. Pinkston, University of Southern California, USA
* Carlo Pistritto, STMicroelectronics, Italy
* Tor Skeie, University of Oslo, Norway
* Vittorio Zaccaria, Politecnico di Milano, Italy




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