[HiPEAC-announce] IISWC 2008 - Call For Participation

[Beckmann, Brad]

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 C A L L    F O R    P A R T C I P A T I O N -- I I S W C   2 0 0 8

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We would like to welcome you to participate in:

The IEEE Intl Symposium on Workload Characterization (IISWC 2008) 

in Seattle, WA, during September 14-16, 2008.

 

The symposium is dedicated to the understanding and characterization 

of workloads across all types of computing systems.  The symposium 

features an exciting technical conference comprising excellent 

papers from a diverse set of areas, two keynote speeches by 

distinguished speakers, and three tutorials.  A summary of the 

program appears below and may also be found at: 

http://www.iiswc.org.

 

Please consider attending!

 

Where: Crowne Plaza Hotel, Seattle, WA, USA

When: September 14-16, 2008

EARLY REGISTRATION DEADLINE: September 4

 

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Program at a glance

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Sunday, September 14

 

Tutorial I:             Transactional Memory for C/C++

Tutorial II:            Fast Simulation without Bogus Results

Tutorial III:           PIN Tutorial

 

Monday, September 15

 

8:00 a.m. - 8:30 a.m.   Breakfast

8:30 a.m. - 8:45 a.m.   Welcome

8:45 a.m. - 9:45 a.m.   Keynote Speech I (TBD)

10:15 a.m. - 11:45 a.m. Session 1: Multi-core Systems

11:45 a.m. - 1:15 p.m.  Lunch

1:15 p.m. - 2:45 p.m.   Session 2: Benchmarks and Runtimes for Thread
Parallelism

3:15 p.m. - 4:45 p.m.   Session 3: Emerging Workloads

 

Tuesday, September 16

 

8:00 a.m. - 8:45 a.m.   Breakfast

8:45 a.m. -9:45 a.m.    Keynote Speech II (TBD)

10:15 a.m. - 11:45 a.m. Session 4: Commercial Workloads

11:45 a.m. - 1:15 p.m.  Lunch

1:15 p.m. - 2:15 p.m.   Session 5: Architecture Issues

2:45 p.m. - 4:15 p.m.   Session 6: Workload Fidelity

 

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Detailed technical program

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Sunday, September 14

 

Tutorial I:       Transactional Memory for C/C++ ++: Design,
Implementation and Performance

 - Presenters: Adam Welc, Yang Ni, and Ali-Reza Adl-Tabatabai (Intel
Corporation)

 

Tutorial II:      Fast Simulation without Bogus Results : Fast
Simulation without Bogus Results

 - Presenters: Tom Conte, Paul Bryan (Georgia Institute of Technology)

 

Tutorial III:     PIN Tutorial

 - Presenter: Aamer Jaleel (Intel Corporation)

 

Monday, September 15

 

8:00 a.m. - 8:30 a.m.   Breakfast

 

8:30 a.m. - 8:45 a.m.   Welcome

 

8:45 a.m. - 9:45 a.m.   Keynote Speech I (TBD)

 

10:15 a.m. - 11:45 a.m. Session 1: Multi-core Systems

 

Energy-Aware Application Scheduling on a Heterogeneous Multi-core
System, Jian Chen (UT-Austin) Lizy K. John (UT-Austin) 

 

Parallelization and Characterization of SIFT on Multi-Core Systems, Hao
Feng (Intel China Research Center) Eric Li (Intel China Research Center)
Yurong Chen (Intel China Research Center) Yimin Zhang (Intel China
Research Center) 

 

Implications of Cache Asymmetry on Server Consolidation Performance,
Padma Apparao (Intel Corporation) Ravi Iyer (Intel 

Corporation) Don Newell (Intel Corporation)

 

11:45 a.m. - 1:15 p.m.  Lunch

 

1:15 p.m. - 2:45 p.m.   Session 2: Benchmarks and Runtimes for Thread
Parallelism

 

BenchTM: Benchmarking Transactional Memory, Chi Cao Minh (Stanford
University) JaeWoong Chung (Stanford University) Christos Kozyrakis
(Stanford University) Kunle Olukotun (Stanford University) 

 

PARSEC vs. SPLASH-2: A Quantitative Comparison of Two Multithreaded
Benchmark Suites on Chip-Multiprocessors, Christian Bienia (Princeton
University) Sanjeev Kumar (Intel Corporation) Kai Li (Princeton
University) 

 

Characterizing and Improving the Performance of The Intel Threading
Building Blocks Runtime Library, Gilberto Contreras (Princeton
University) Margaret Martonosi (Princeton University)

 

3:15 p.m. - 4:45 p.m.   Session 3: Emerging Workloads

 

Whiteboards that Compute: An Analysis of the Performance Challenges
Ahead, Ryan Dixon (University of California, Santa Barbara) Timothy
Sherwood (University of California, Santa Barbara) 

 

A workload for evaluating deep packet inspection architectures, Michela
Becchi (Washington University) Mark Franklin (Washington University)
Patrick Crowley (Washington University) 

 

Empirical Examination of A Collaborative Web Application, Matthew
Leventi (Univ of Rochester) Christopher Stewart (Univ of Rochester) Kai
Shen (Univ of Rochester)

  

 

Tuesday, September 16

 

8:00 a.m. - 8:45 a.m.   Breakfast

 

8:45 a.m. -9:45 a.m.    Keynote Speech II (TBD)

 

10:15 a.m. - 11:45 a.m. Session 4: Commercial Workloads

 

Temporal Streams in Commercial Server Applications, Thomas Wenisch
(University of Michigan) Michael Ferdman (Carnegie Mellon University)
Anastasia Ailamaki (Carnegie Mellon & EPFL) Babak Falsafi (Carnegie
Mellon & EPFL) Andreas Moshovos (University of Toronto) 

 

Workload Characterization of selected JEE-based Web 2.0 Applications,
Priya Nagpurkar (IBM TJ Watson Research Center) William P Horn (IBM TJ
Watson Research Center) U Gopalakrishnan (IBM TJ Watson Research Center)
Pratap Pattnaik (IBM TJ Watson Research Center) 

 

Characterization of Storage Workload Traces from Production Windows
Servers, Bruce Worthington (Microsoft Corporation) Swaroop Kavalanekar
(Microsoft Corporation)

 

11:45 a.m. - 1:15 p.m.  Lunch

 

1:15 p.m. - 2:15 p.m.   Session 5: Architecture Issues

 

Evaluating the Impact of Dynamic Binary Translation Systems on Hardware
Cache Performance, Arkaitz Ruiz Alvarez (University of Virginia) Kim
Hazelwood (University of Virginia) 

 

Can Hardware Performance Counters be Trusted? Vincent M. Weaver (Cornell
University) Sally A. McKee (Cornell University)

 

2:45 p.m. - 4:15 p.m.   Session 6: Workload Fidelity

 

On the Representativeness of Embedded Java Benchmarks, Ciji Isen
(University of Texas at Austin, ECE Dept) Lizy John (University of Texas
at Austin, ECE Dept) 

 

Accelerating Multi-core Processor Design Space Evaluation Using
Automatic Multi-threaded Workload Synthesis, Clay Hughes (University of
Florida) Tao Li (University of Florida) 

 

Reproducible Simulation of Multi-Threaded Workloads for Architecture
Design Exploration, Cristiano Pereira (Intel Corporation & Univesity of
California, San Diego) Harish Patil (Intel Corporation) Brad Calder
(Microsoft Corporation & University of California, San Diego)

 

Best regards,

IISWC 2008

 

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