[HiPEAC-announce] 2nd CfP: HipHaC'08 -- First International Workshop on New Frontiers in High-performance and Hardware-aware Computing (in conjunction w/ MICRO-41)

[Rainer Buchty]

[Our apologies if you receive multiple copies of this CFP]

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                     2nd Call for Papers:  HipHaC'08
                     First International Workshop on 
      New Frontiers in High-performance and Hardware-aware Computing
                     To be held in conjunction with
  the 41st Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-41)
                             November 8, 2008
                             Lake Como, Italy
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General Information
-------------------

Heterogeneity and reconfigurability in computer systems is growing. Multi-
and manycore-based systems are complemented by coprocessors, accelerators
and reconfigurable units providing huge computational power. However,
applications of scientific interest (e.g. in high-performance computing and
numerical simulation) are not yet ready to exploit the available high
computing potential. Different programming models, non-adjusted interfaces,
and bandwidth bottlenecks complicate holistic programming approaches for
heterogeneous architectures. In modern microprocessors, hierarchical memory
layouts and complex logics obscure predictability of memory transfers or
performance estimations.

For efficient implementations and optimal results, underlying algorithms and
mathematical solution methods have to be adapted carefully to architectural
constraints like fine-grained parallelism and memory or bandwidth
limitations that require additional communication and synchronization.
Currently, a comprehensive knowledge of underlying hardware is therefore
mandatory for application programmers. Hence, there is strong need for
virtualization concepts that free programmers from hardware details,
maintaining best performance and enable deployment in heterogeneous and
reconfigurable environments.

Possible solutions may consist of supporting libraries, software layers, and
tools that automatically care for adaptations of program parameters like
block sizes or communication patterns. Autotuning concepts are a possible
approach for finding non-obvious optimal choices of such parameters.

This workshop aims at combining new aspects of parallel, heterogeneous, and
reconfigurable microprocessor technologies with concepts of high-performance
computing and, particularly, numerical solution methods. Compute- and
memory-intensive applications can only benefit from the full hardware
potential if all features on all levels are taken into account in a holistic
approach. 


Topics of interest for workshop submissions include (but are not limited to):
------------------

* Emerging hardware architectures (Multicores, Cell BE, GPUs, FPGAs, ...)
* High-performance heterogeneous, adaptive, and reconfigurable
  architectures
* Parallelization strategies in hybrid and hierarchical setups
* Hardware-aware computing and code optimization strategies
* Virtualization and software layers for heterogeneous and
  reconfigurable platforms freeing programmers from dedicated hardware
  knowledge
* Architecture-aware approaches for parallel numerical applications,
  implementation, and algorithm design
* Programming models, compiler techniques, and code optimization
  strategies for parallel systems
* Autotuning concepts and run-time adaptivity
* Practice and experience of multicore programming
* Performance evaluation of scientific applications on emerging hardware
* Tools for design, programming, and optimization


Submission guidelines:
----------------------
You are invited to submit papers not exceeding 8 double-column IEEE
formatted pages (including up to 6 keywords and an abstract of no more than
350 words), describing original, unpublished recent work related to the
workshop theme. Submission must be in PDF format and emailed to

	submission at hiphac.org

If you wish a blind review to be performed, do not include the author's name
and affiliation in the paper. In case of any questions please contact the
workshop organizers.

The selected papers will be published as printed workshop proceedings
through Karlsruhe University Press.


Important Dates:
----------------
Paper Submission Deadline:      September 1, 2008
Notification of Acceptance:     September 29, 2008
Camera-ready Papers:            October 10, 2008
HipHaC Workshop:		November 8, 2008


Organizers
----------
Rainer Buchty, Karlsruhe Institute of Technology, Germany
(rainer.buchty at kit.edu)

Jan-Philipp Weiß, Karlsruhe Institute of Technology, Germany
(jan-philipp.weiss at kit.edu)


Steering Committee
------------------
Jürgen Becker, Karlsruhe Institute of Technology, Germany
Vincent Heuveline, Karlsruhe Institute of Technology, Germany
Wolfgang Karl, Karlsruhe Institute of Technology, Germany
Jan-Philipp Weiß, Karlsruhe Institute of Technology, Germany


Program Committee
-----------------
Jürgen Becker, Karlsruhe Institute of Technology, Germany
Mladen Berekovic, Univ. Braunschweig, Germany
Alan Berenbaum, SMSC, USA
Nevin Heintze, Google Inc.
Vincent Heuveline, Karlsruhe Institute of Technology, Germany
Eric D'Hollander, Ghent University, Belgium
Ben Juurlink, TU Delft, The Netherlands
Paul Kelly, Imperial College, UK
Wolfgang Karl, Karlsruhe Institute of Technology, Germany
Richard Kaufmann, Hewlett-Packard, USA
Hsin-Ying Lin, Intel, USA
Scott McClellan, Hewlett-Packard, USA
Andy Nisbet, Manchester Metropolitan University, UK
Ulrich Rüde, Universität Erlangen-Nürnberg, Germany
Martin Schulz, LLNL, USA
Thomas Steinke, Zuse-Institut Berlin, Germany
Robert Strzodka, Max Planck Institut Informatik, Germany
Stephan Wong, TU Delft, The Netherlands


Electronic Information
---------------------- 
Workshop Flyer with all information:
	http://www.hiphac.org/flyer/

Workshop Website with all information:
	http://www.hiphac.org