[HiPEAC-announce] Workshop on Interconnection Networks - deadline extended!

[Olav Lysne]

Submission deadline extended: Oct 22, 2007!!

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                               CALL FOR PAPERS

Workshop on Interconnection Network Architectures: On-Chip, Multi- 
Chip (INA-OCMC)
                (http://www.disca.upv.es/jflich/wina/wina.html)

                           Held in conjunction with
            the 3rd International Conference on High-Performance  
Embedded
        Architectures and Compilers (HiPEAC) (http://www.hipeac.net/ 
conference)
                     in Goteborg, Sweden, January 27, 2008

Organizers:
- Jose Duato, Technical University of Valencia, Spain (General Co-Chair)
- Jose Flich, Technical University of Valencia, Spain (General Co-Chair)
- Olav Lysne, Simula Research Laboratory, Norway (Program Chair)

The solutions for communication between components within embedded
and parallel systems is undergoing rapid development.  The move to
multi-core chips force programmers to develop parallel applications,
and thus demand novel solutions to how cores on a chip should  
communicate
between them. At the other end of the scale, parallel supercomputers
with tens of thousands of processors demand new and scalable solutions
to interconnections of its components.

This workshop concerns the architecture of interconnection
switches or routers, and networks of switches or routers, whether
on-chip or multi-chip. Topics of interest, within the context of
interconnection networks, include but are not limited to:

  * Networks-on-Chip (NoC)
  * Multi-Chip Interconnection Networks, including Cluster Interconnects
  * "Commodity Switches" as general-purpose building blocks
  * Switching, buffering, and routing architectures
  * Flow control and congestion management in switching fabrics
  * Virtualization
  * Topology exploration
  * Timing, synchronous/asynchronous communication
  * Reliability, availability, fault tolerance
  * Area/power versus functionality/QoS support in NoC architectures
  * Design space exploration

The goal of the workshop is to provide a forum for presenting and
discussing mostly work in progress, or ideas for future research
in response to future trends. The workshop intends to include a
couple of presentations by experts in the field about the current
state-of-the-art and where we need to go, and intends to encourage
discussions among the participants. It does not matter if the
views and opinions expressed are "wild and crazy", as long as they
have been carefully thought out and they are intuitively sound
and implementable.

This is the second year of the workshop. In its first year the workshop
exhibited a high audience and interesting discussions arose from the  
different
presentations of authors.

Program Committee:
- Olav Lysne, Simula Research Laboratory
- Francisco Alfaro,  UCLM, Spain
- Luca Benini, University of Bologna, Italy
- Davide Bertozzi, University of Bologna, Italy
- Ulrich Bruning, U. Mannheim, Germany
- Ran Ginosar, Technion, Israel	
- Kees Goossens , NXP and T.U.Delft, The Netherlands
- Wojciech Kabacinski, Poznan University of Technology, Poland
- Manolis Katevenis, FORTH, Greece
- Hugo Kohmann, Dolphin Interconnect Solutions, Norway
- Cyriel Minkenberg, IBM Zurich Research Laboratory, Switzerland
- Robert Mullins, Cambridge University, United Kingdom UK
- Dionisios Pnevmatikatos, FORTH-ICS and Techn. Univ. of Crete, Greece
- Jose Luis Sanchez, UCLM, Spain
- Thomas Sodring, Simula Research Laboratory, Norway
- Ola Torudbakken, SUN, Norway
	
Submissions and acceptance will be in the form of extended abstracts
of length 3-5 pages. The submission procedure will be through the EDAS
web-page (http://www.disca.upv.es/jflich/wina/wina.html). There will  
be no Proceedings,
but we will encourage authors to electronically share their texts
and slides with all participants.

Important dates:
- Submission deadline: Oct 22, 2007 *extended* (no further extensions  
will be given)
- Notification to authors: Dec 1, 2007

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