[HiPEAC-announce] Call for Participation HiPEAC 2008

[hipeac2008 at gso.ac.upc.edu]

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				HiPEAC 2008

                         CALL-FOR-PARTICIPATION


2008 International Conference on High Performance Embedded Architectures & Compilers
                    Goteborg, SWEDEN, January 27-29, 2008

                     http://www.hipeac.net/conference


	IMPORTANT DATES: Pre-registration deadline: December 17, 2007





Program for HiPEAC 2008

MONDAY, January 28, 2008
8:45 - 9:00 OPENING 

9:00 - 10:00 KEYNOTE. Supercomputing for the Future, Supercomputing from the Past 
Mateo Valero, Barcelona Supercomputing Center 

10:00 - 10:30 COFFEE BREAK 

10:30 - 12:00 
SESSION I. Multithreaded and Multicore Processors 
CHAIR: Georgi Gaydadjiev, T. U. Delft, Netherlands  

MIPS MT: A Multithreaded RISC Architecture for Embedded and Real-Time Processing 
Kevin D. Kissell 
MIPS Technolgies Inc.  

rMPI: Message Passing on Multicore Processors with On-Chip Interconnect 
James Psota and Anant Agarwal 
MIT  

Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE 
Filip Blagojevic, Xizhou Feng, Kirk W. Cameron and Dimitrios S. Nikolopoulos 
Virginia Tech  

12:00-13:30 LUNCH 

13:30 - 15:00 SESSION IIa. Reconfigurable - ASIP 
CHAIR: Chris Gniady, University of Arizona, USA  
BRAM-LUT tradeoff on a Polymorphic DES Design 
Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa and Stamatis Vassiliadis 
Instituto Superior Tecnoci/INESC-ID and TUDelft  

Architecture Enhancements For The ADRES Coarse-Grained Reconfigurable Array 
Frank Bouwens, Mladen Berekovic and Georgi Gaydadjiev 
IMEC and TUDelft  

Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP 
Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael de Nil and Jef van Meerbergen 
Eindhoven University of Technology, IMEC, Philips Research Eindhoven and Silicon Hive  

13:30 - 15:00 SESSION IIb. Compiler Optimizations 
CHAIR: Koen De Bosschere, University of Ghent, Belgium  

Fast Bounds Checking Using Debug Register 
Tzi-cker Chiueh 
Stony Brook University  

Studying Compiler Optimizations on Superscalar Processors through Interval Analysis 
Stijn Eyerman, Lieven Eeckhout and James E. Smith 
Ghent University and University of Wisconsin-Madison  

An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems 
Marco Cornero, Roberto Costa, Ricardo Fernandez Pascual, Andrea Ornstein and Erven Rohou 
STMicroelectronics  

15:00 - 15:30 COFFEE BREAK 

15:30 - 17:00 SESSION III. Industrial Processors & Application Parallelization 
CHAIR: Mike O'Boyle, Edinburgh University, UK  

Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions 
Todd Hahn, Dineel Sule, Eric Stotzer and Mike Asal 
Texas Instruments  

Experiences with Parallelizing a Bio-Informatics Program on the Cell BE 
Hans Vandierendonck, Sean Rul, Michiel Questier and Koen De Bosschere 
Ghent University  

Drug Design Issues on the Cell BE 
Harald Servat , Cecilia Gonzalez-Alvarez , Xavier Aguilar, Daniel Cabrera-Benitez and Daniel Jimenez-Gonzalez 
Barcelona Supercomputing Center and Universitat Politecnica de Catalunya  

17:00 - 18:00 HiPEAC Internships meeting 


Tuesday, January 29, 2008

8:30 - 10:00 
SESSION IV. Power-Aware Techniques 
CHAIR: Mats Brorsson, KTH, Sweden  

COFFEE: COmpiler Framework For Energy-aware Exploration 
Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor and Diederik Verkest 
KULeuven, IMEC, STMicroelectronics and VUB  

Integrated CPU and Cache Power Management in Multiple Clock Domain Processors 
Nevine AbouGhazaleh, Bruce Childers, Daniel Mosse and Rami Melhem 
University of Pittsburgh  

Variation-Aware Software Techniques for Cache Leakage Reduction using Value-Dependence of SRAM Leakage due to Within-Die Process Variation 
Maziar Goudarzi, Tohru Ishihara and Hamid Noori 
Kyushu University  

10:00 - 10:30 COFFEE BREAK 
10:30 - 12:00 
SESSION V. High-Performance Processors 
CHAIR: Kevin Kissell, MIPS Technolgies Inc., France  

The Significance of Affectors and Affectees Correlations for Branch Prediction 
Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides and Marios Kleanthous 
University of Cyprus and University of Michigan  

Turbo-ROB: A Low-Cost, Simple Checkpoint/Restore Accelerator 
Patrick Akl and Andreas Moshovos 
University of Toronto  

LPA: A First Approach to the Loop Processor Architecture 
Alejandro Garcia, Oliverio J. Santana, Enrique Fernandez, Pedro Medina and Mateo Valero 
Barcelona Supercomputing Center, University Politecnica de Catalunya and Universidad de Las Palmas de Gran Canaria  

12:00-13:30 LUNCH 
13:30 - 15:00 SESSION VI. Profiles: Collection and Analysis
CHAIR: Dimitrios Nikolopoulos, FORTH, Crete, Greece  

Complementing Missing and Inaccurate Profiling using a Minimum Cost Circulation Algorithm 
Roy Levin, Gad Haber and Ilan Newman 
Haifa University and IBM Haifa Labs  

Using Dynamic Binary Instrumentation to Generate Multi-Platform SimPoints: Methodology and Accuracy 
Vincent M. Weaver and Sally A. McKee 
Cornell University  

Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior 
Frederik Vandeputte and Lieven Eeckhout 
Ghent University  

15:00 - 15:30 COFFEE BREAK 

15:30 - 17:30 SESSION VII. Optimizing Memory Performance 
CHAIR: Andreas Moshovos, University of Toronto, Canada  

MLP-Aware Dynamic Cache Partitioning 
Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero 
Barcelona Supercomputing Center and Universitat Politecnica de Catalunya  

Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture 
Subhradyuti Sarkar and Dean M. Tullsen 
UCSD  

Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory 
Chun-Chieh Lin and Chuen-Liang Chen 
National Taiwan University  

Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache 
Yosi Ben Asher, Omer Boehm, Daniel Citron, Gadi Haber, Moshe Klausner, Roy Levin and Yousef Shajrawi 
Haifa University and IBM Research Lab, Haifa  



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