[HiPEAC-announce] Call For Participation: 2nd HiPEAC Workshop on Reconfigurable Computing 2008

[Ioannis Sourdis]

Please accept our apologies if you receive multiple copies of this CFP.

DUE TO SEVERAL EVENTS IN GOTEBORG BETWEEN JAN 27 - FEB 1, 2008, IT IS
IMPORTANT THAT YOU MAKE HOTEL RESERVATIONS EARLY!

                        		Call For Participation - WRC 2008

                    *Second HiPEAC Workshop on Reconfigurable Computing*

		
				January 27, 2008
				Goteborg, Sweden

                        http://ce.et.tudelft.nl/HiPEACRC_WS/

The HiPEAC Workshop on Reconfigurable Computing provides a forum for
researchers active in domains within the reconfigurable computing area.
Its main focus is on reconfigurable *architectures*, *tools* that
facilitate such architectures, and *applications* tailored for
reconfigurable platforms. The workshop intends to bring together both
hardware designers and software developers that make extensive use of
reconfigurable computing. Moreover, it aims at enabling scientific
discussions regarding future challenging issues.

==========================================================================
*PRELIMINARY PROGRAM*

09:00-09:10 Opening remarks
09:10-10:10 *Keynote session (Keynote Speaker Prof. Wayne Luk, Imperial
College London)*
10:10-10:40 Coffee break
10:50-11:50 SESSION 1: *PARTIAL RECONFIGURATION*

Dynamic Partial Self-Reconfiguration on Spartan-III FPGAs via a Parallel
Configuration Access Port (PCAP),
Salih Bayar and Arda Yurdakul,
Bogazici University, Turkey.

Performance Evaluation of Partially Reconfigurable Computing Systems
Foad Lotfifar and Hadi Shahriar Shahhoseini,
Iran University of Science and Technology, Iran.

12:00-13:30 Lunch
13:40-15:10 SESSION 2: *MULTICORES & INTERCONNECTS*

Rapid Prototyping of the Data-Driven Multithreading Chip-Multiprocessor
using FPGAs,
Konstantinos Tatas, Costas Kyriacou, Stephan Wong, Pedro Trancoso and
Paraskevas Evripidou,
Frederick University Cyprus, Cyprus University & TU Delft, The Netherlands.

Architecture and Implementation of Traffic Shaper Integrating
Networks-on-Chip and off-chip Networks,
George Kornaros, Theofanis Orphanoudakis and Helen-Catherine Leligou,
TU Crete & NTUA, Greece.

A High-Throughput, Write-Only On-Chip Bus for FPSoCs,
Guenter Knittel,
Tuebingen University, Germany. 	

15:10-15:40 Coffee break
15:40-17:40 SESSION 3: *TOOLS & APPLICATIONS*

Building an Application Specific Memory Hierarchy on FPGA,
Harald Devos, Jan Van Campenhout and Dirk Stroobandt,
Ghent University, Belgium.

FPGA Implementation of Parallel Histogram Computation,
Asadollah Shahbahrami, Jae Young Hur, Ben Juurlink and Stephan Wong,
TU Delft, The Netherlands.

Quantitative Evaluation of Behavioral Synthesis Approaches for
Reconfigurable Devices,
Frank Hannig, Hritam Dutta, Holger Ruckdeschel and Jurgen Teich,
University of Erlangen-Nuremberg, Germany.

Profile-directed speculative optimization of reconfigurable floating
point data paths,
Ashley W. Brown, Wayne Luk and Paul Kelly,
Imperial College London, UK.

17:40-17:50 Closing

==========================================================================
*Registration Information*

All registrations should be done through the HiPEAC conference website:
http://www.hipeac.net/conference/

early registration until December 17th
==========================================================================


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Ioannis Sourdis                   URL: http://ce.et.tudelft.nl/~sourdis/
CE Lab,Electrical Engineering Dept.            Phone: +31 (0)15 278 9656
Delft University of Technology                 Fax:   +31 (0)15 278 4898
Mekelweg 4, 2628 CD Delft, The Netherlands
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