HiPEAC partners
Ghent University
Ghent University is the second biggest University of Belgium, with 27 000 students and an annual research budget of over 350 M€. The Parallel Information Systems (PARIS) research group of the department of Electronics and Information Systems of the Ghent University is the Centre of excellence on computing systems of the Ghent University. It consists of 40 members, 10 of them at the post-doc level. Over the last 10 years, the group has produced over 300 refereed publications and 20 PhDs. Graduates of the research group can be found in leading companies like Intel, HP, Belgacom, Barco, and Synopsis. PARIS is coordinator of the Belgian ACES research network (Architectures and Compilers for Embedded Systems), and partner in the FP6 SARC project and HiPEAC NoE. PARIS has active collaborations with leading American research groups at the University of Texas at Austin, the University of Wisconsin-Madison, the University of Arizona, the University of California, San Diego, IBM ISRAEL T.J. Watson, … The PARIS research group has recognised expertise in binary translation (Diablo framework), dynamic code optimization and virtualization, microprocessor performance modeling, workload characterization, fast simulation techniques, and reconfigurable computing.
Staff member
Koen De Bosschere is research professor at the Engineering Faculty of Ghent University where he teaches courses on computer architecture and operating systems. He is the head of a research group of 20 researchers active in the domain of computer architecture, compilation and operating systems. He is author of 140 publications over the last 10 years. In 2004 he was awarded the Francqui Chair on Software Optimization of Embedded Systems at the University of Namur. He is member of the computer science advisory board of the Fund for Scientific Research - Flanders and he is coordinator of the Flemish network of computer architecture and compilation.
Tasks
Leader of the management work package, coordinator of the binary translation and virtualization cluster, summer school, reimbursement service, technical staff, administrative staff, award program.
RWTH Aachen University
RWTH Aachen University, Germany, is an internationally top-ranked technical university with around 30,000 students and is a member of the IDEA league. Its Institute for Integrated Signal Processing Systems (ISS), being part of the RWTH Department of Electrical and Computer Engineering, is headed by Prof. R. Leupers, Prof. G. Ascheid, and Prof. H. Meyr. ISS performs research and development in different areas of embedded system design technology, especially covering algorithms, architectures, and tools for wireless communication systems. ISS maintains tight cooperations with semiconductor vendors, system houses, and EDA companies, and frequently provides industrial consulting services. ISS receives funds from the Deutsche Forschungsgemeinsschaft (DFG), e.g. via the new Excellence Cluster UMIC (Ultra High Speed Mobile Information and Communication), a large scale next-generation mobile internet research program. Further funding is received from EU FP6 projects like SHAPES, HiPEAC1, and NEWCOM, as well as from industry partners like Siemens, Nokia, Infineon, CoWare, ACE, and Tokyo Electron. Many R&D projects at ISS have contributed to the development of industrial products. Moreover, several successful EDA spin-off originated from the ISS, e.g. Cadis (acquired by Synopsys), Axys (acquired by ARM), and LISATek (acquired by CoWare).
Staff member
Rainer Leupers received Diploma and Ph.D. degrees in Computer Science with honors from the University of Dortmund, Germany, in 1992 and 1997. From 1997-2001 he was the chief engineer at the Embedded Systems group at the University of Dortmund. During 1999-2001 he was also a project manager at ICD, where he headed industrial consulting projects. In 2002, Dr. Leupers joined RWTH Aachen University as a professor for Software for Systems on Silicon. His research and teaching activities comprise software development tools, processor architectures, and electronic design automation for embedded systems, with emphasis on compilers, ASIPs, and MPSoC design tools. He authored several books and numerous technical papers, and he served as program committee member and topic chair of leading scientific conferences, including DAC, DATE, and ICCAD. Dr. Leupers received several research awards, including Best Paper Awards at DATE 2000 and DAC 2002. He has been a co-founder of LISATek, an EDA tool provider for embedded processor design, acquired by CoWare Inc. in 2003.
Tasks
Coordinator of the design methodology and tools cluster, newsletter.
Barcelona Supercomputing Center
The Barcelona Supercomputing Center-Centro Nacional de Supercomputación (BSC-CNS), established in 2005, serves as the National Supercomputing Facility in Spain. The Center hosts MareNostrum, the most powerful supercomputer in Europe which is ranked the fifth most powerful in the world according to the Top500 list published in November 2006. The mission of the BSC-CNS is to research, develop and manage information technologies in order to facilitate scientific progress. The BSC-CNS not only strives to become a first-class research center in supercomputing, but also in scientific fields that demand high performance computing resources such as the Life and Earth Sciences. Following this approach, the BSC-CNS has brought together a critical mass of top-notch researchers, high performance computing experts and cutting-edge supercomputing technologies in order to foster multidisciplinary scientific collaboration and innovation.
The Computer Sciences Department of the BSC-CNS focuses on building upon currently available hardware and software technologies and adapting them to make efficient use of supercomputing infrastructures. The department proposes novel architectures for processors and memory hierarchies and develops programming models and innovative implementation approaches for these models as well as tools for performance analysis and prediction. In addition, the department is working on resource management at various component levels (processor, memory, and storage) and for different execution environments, including Grid and e-Business platforms and application optimization
Staff member
Mateo Valero obtained his PhD at UPC in 1980. He is a professor in the Computer Architecture Department at UPC. His research interests focus on high performance architectures. He has published approximately 400 papers on these topics. He is the director of the Barcelona Supercomputing Center, the National Center of Supercomputing in Spain. Dr. Valero has been honored with several awards, including the King Jaime I by the Generalitat Valenciana, and the Spanish National awards "Julio Rey Pastor" in 2001, to recognize research on IT technologies, and the “Leonardo Torres Quevedo” in 2006, to recognize research in Engineering, by the Spanish Ministry of Science and Technology, presented by the King of Spain.
In December 1994, Professor Valero became a founding member of the Royal Spanish Academy of Engineering. In 2005 he was elected Correspondent Academic of the Spanish Royal Academy of Science and in 2006, member of the Royal Spanish Academy of Doctors. In 2000 he became a Fellow of the IEEE. In 2002, he became an Intel Distinguished Research Fellow and a Fellow of the ACM, the Association for Computing Machinery. In 1998 he won a “Favorite Son” Award of his home town, Alfamén (Zaragoza) and in 2006, his native town of Alfamén named their Public College after him.
Tasks
Coordinator of the programming models and operating systems cluster, membership management, mini-sabbaticals, web seminars.
Chalmers University of Technology
The High-Performance Computer Architecture Group at Chalmers is primarily concerned with how to design future computer systems aimed at the embedded as well as at the high-end computing market. A key focus is on design principles and methods for multi-threaded processor architectures, memory systems, and performance evaluation methodologies. The focus of the research over the last 10-15 years has been on design principles for exploiting coarse-grained or thread-level parallelism in multiprocessors - a topic of perhaps higher relevance than ever today as microprocessors start to exploit thread-level parallelism. We have contributed with a hundred international publications on cache coherence schemes, latency-tolerance techniques in multiprocessors using pre-fetching and relaxed memory consistency models and lately techniques to implement thread-level speculation. Lately, we have also paid attention to design issues for embedded systems, e.g., architectural tradeoffs to meet hard real-time and energy-effective demands.
Current work focuses on the following topics:
Processor architecture. We are considering design principles for chip-multiprocessor systems, especially thread level speculation techniques and design principles for energy-effective on-chip memory systems. This work involves collaboration with Ericsson Mobile Platforms (Lund, Sweden) as well as Sun Microsystems (Menlo Park, U.S.A.).
Memory systems. As the gap between processor, memory, and disk speed is widening, the amount of memory resources in the machine increases and more power consumption is tied to the memory system. We are investigating techniques to more effectively use memory resources through e.g. compression to cut down on power consumption and to reduce the speed gap. We are collaborating with Ericsson and Sun Microsystems on this topic.
Adaptable SoCs. We have also launched FlexSoC - a project that aims at taking a radically new view on the design of instruction-set architectures to ease the hardware/software codesign of System-on-Chips. This project involves seven faculty members and PhD students in compiler design, computer architecture, and VLSI design. We are collaborating with Ericsson and Axis Communications on this topic.
Simulation methodologies. The group has also developed, or has been part of the development of, a number of influential computer system simulation tools such as the CacheMire Test Bench, Simics, and SimWattch, where CacheMire was one of the first entirely software-based multiprocessor simulation systems; Simics was the first commercially available complete-system simulation tool, and SimWattch a tool that combines system-level with micro-architecture level simulation tools to estimate performance as well as power-consumption.
The scientific output of the group counts more than a hundred publications in refereed international journals and conferences. Per Stenstrom – the group leader – is a very active and respected leader in the research community; he is editor of IEEE Computer Architecture Letters, Journal of Parallel and Distributed Computing and editor-in-chief for the HiPEAC journal, has been member of program committees over 50 times in the last ten years. Among other chairmanships, he was the general chair of IEEE/ACM International Symposium on Computer Architecture in 2001 and is its program chair in 2004 - the top conference in the field. He acted as program chair and general chair for the HiPEAC conference series in 2006 and 2008, respectively. He is a Fellow of the IEEE and a member of ACM.
Staff member
Per Stenström is a Professor of Computer Engineering at Chalmers University of Technology and Deputy Dean of the IT University of Goteborg. His research interests are devoted to design principles for high-performance computer systems. He is an author of two textbooks and a hundred research publications. He has served on more than 50 program committees of major conferences in the computer architecture field and is an editor of IEEE Trans. on Computers and the Journal of Parallel and Distributed Computing. He has served as General as well as Program Chair of the ACM/IEEE Int. Symposium on Computer Architecture. He is a Fellow of the IEEE and a member of the ACM.
Tasks
Leader of the spreading excellence program work package, coordinator of the multi-core architecture cluster, conference, journal.Delft University
The Computer Engineering Laboratory performs research and teaches the engineering discipline of how to determine, develop, and integrate software and hardware to build a computing system. The laboratory focuses on the definition of system requirements, from embedded to general purpose, their architecture and implementations, and the study and development of tools and software that allow improving the analysis and synthesis of computing systems. More precisely, the laboratory is actively involved in: computer architecture, machine organizations, and network processing, mapping of application and algorithm requirements to architectures of embedded systems (e.g. multimedia), compiler technology capable of directing system requirements to architectural definitions and improve implementations, architectural synthesis tools for semi-automatic implementation of architectures, computer arithmetic and logic design, algorithms and tools for testing memories, built in self-test of logic circuits, and automatic test pattern generation for combinational and sequential logic circuits. The laboratory also researches performance modeling and optimization techniques and tools. The CE Lab has extensively and successfully been involved in various research and industrial projects on embedded systems. A major outcome of this research is the Molen architecture, which is a polymorphic processor paradigm that addresses the fundamental issues in combining general-purpose processors with custom computing processing (such as FPGAs). An implementation of the Molen processor has been developed and additional tools, such as back end compilers and code profilers, are in the process of being developed. The Molen platform is used as a base in two big FP6 IP projects: MORPHEUS and hArtes.
Most of the funded research comes from the STW (Dutch national science foundation) and the industry: Philips, IBM ISRAEL, Intel, Nokia, etc. 12 start-up companies have been founded by ex-students and computer engineering faculty members. The laboratory formation, which will participate in the NoE, includes 8 faculty members, 2 staff members, 4 postdocs, 51 PhD students, and 33 MSc students.
In the past 10 years, the scientific output of the group counts 425 publications in refereed international top conferences and 87 papers in high-level journals in the field. The group is very active and respected in the research community; the majority of the top conferences include members of the group on various levels ranging from general and program chairs to PC members and reviewers. CE is the founder and main organizer of the yearly SAMOS symposium that is becoming one of the important venues in the field of Embedded Computer Systems, Modeling and Simulation.
Staff member
Georgi N. Gaydadjiev is assistant professor in the Computer Engineering Laboratory, Delft University of Technology, the Netherlands. His research and development experience includes 15 years in hardware and software design at System Engineering Ltd. in Pravetz, Bulgaria, and Pijnenburg Microelectronics and Software B.V. in Vught, the Netherlands. His research interests include embedded systems design, advanced computer architectures, hardware/software codesign, reconfigurable computing, VLSI design, cryptographic systems, and computer systems testing. He is regularly serving program committees of major conferences in the computer architecture field. He has served as General as well as Program Chair of the SAMOS International Conference. He is a member of ACM and IEEE. Georgi participates to, leads or is co-leading several national and European Union funded projects. He has published over 30 papers in international journals and conferences in this area and is currently supervising 10 PhD students on related topics.
Tasks
Coordinator of the configurable systems cluster, innovation letters.
The University of Edinburgh
The School of Informatics at the University of Edinburgh is widely recognized as a world class centre for Computer Science research. Edinburgh was the only University in the UK awarded the top 5*A rating in Computer Science in the 2001 Research Assessment Exercise. With 87 research active staff submitted for assessment, we are also the UK's biggest research group in this area.
The proposed research is to be carried out at the Institute for Computing Systems Architecture (ICSA). ICSA has a vibrant research community with over 30 PhD students and an extensive research record in several areas directly related to this project: adaptive compilation, automatic parallelizing compilation and low power embedded architectures.
ICSA has taken part in many EU and UK funded projects and has extensive links with local silicon intellectual property companies and the Systems Level Integration (SLI) Institute located nearby in Livingston. Our objective is to develop innovative compiler and architectural proposals that optimize a given requirement such as performance, power or space subject to constraints such as real-time response. These proposals are empirically validated by building prototypes and simulators and eventually lead to technology transfer to industry...
Staff member
Michael O'Boyle is Professor of Computer Science in the School of Informatics at the University of Edinburgh. He received his PhD in Computer Science from the University of Manchester in 1992. He was formerly a SERC Postdoctoral Research Fellow, a Visiting Research Scientist at IRISA/INRIA Rennes, a Visiting Research Fellow at the University of Vienna and a Visiting Scholar at Stanford University. More recently he was a Visiting Professor at UPC, Barcelona. Prof. O'Boyle's main research interests are in adaptive compilation, formal program transformation representations, the compiler impact on embedded systems, compiler directed low power optimization and automatic compilation for parallel single-address space architectures. He has published over 50 papers in international journals and conferences in this area.
Prof O'Boyle has extensive project management experience. Since 1992 he has successfully managed a total of 14 EU and UK projects totaling over 20 M€. All of these projects have been successfully managed to their conclusion. He is currently coordinator for the STREP MilePost and has considerable experience in building a research community in Europe in the area of compilation. He is currently Deputy Director of the Institute for Computing Systems Architecture at the University of Edinburgh. This Institute covers all the systems research conducted at the UK's leading computer science research University. He is also chair of the School of Informatics Research Committee with oversight of the School's large and diverse research portfolio. He is the academic and research leader of the compiler and architecture design group. This 19 strong group includes 5 faculty members, 4 post-doc researchers and 10 PhD students.
Tasks
Leader of the mobility program work package, coordinator of the adaptive compilation cluster, collaboration grants.
FORTH
The Foundation for Research and Technology - Hellas (FORTH) is the premier research center in Greece, internationally acknowledged for its excellence in basic and applied research, in developing applications and products, and in providing services. The Institute of Computer Science (ICS), one of the seven Institutes of FORTH, will be contributing to this project. FORTH has a 24-year history of internationally competitive R&D contributions across the fields of Information & Communication Technologies, as well as of academic and industrial cooperation; it has adopted an evolving strategy to promote the commercial exploitation of R&D results by providing services, licensing products to industrial partners, contracting with industrial partners to jointly develop new products, and participating in spin-off companies and joint ventures. FORTH represents Greece in the European Research Consortium for Informatics and Mathematics (ERCIM). The Institute ranked first among all Greek institutes of its field in the 2005 national evaluation.
Contributions to this project will come from the Computer Architecture and VLSI Systems (CARV) Laboratory of FORTH; it has a 20-year history in architecture, hardware, and systems software R&D, with fundamental contributions in interconnection network architectures and in parallel processing on clusters. CARV expertise includes the design, implementation, and test of dozens of innovative ASIC, board, and system software prototypes, as well as development of novel CAD tools.
In interconnection network architectures, under the leadership of prof. Manolis Katevenis, FORTH worked in 1986-92 on fair queueing, backpressure, congestion tolerance, weighted round-robin scheduling, and switch design for multiprocessor interconnection networks. In 1996-98, FORTH led technically an EU project where a 6-million-transistor, 10 Gb/s single-chip 16×16 ATM switch was implemented in 0.35-micron CMOS, featuring credit-based flow control with 32 thousand virtual channels. In the last 10 years, contributions were in wormhole IP over ATM, pipelined heap management for multi-gigabit weighted fair queueing, implementing thousands of queues in DRAM at 10 Gb/s rate, congestion elimination in switching fabrics with internal backpressure, distributed scheduling in buffered crossbars, and approaching ideally low latency in networks-on-chip (NoC).
In cluster multiprocessor architectures, FORTH has a 14-year history: in the Telegraphos project (1993-95), workstation clustering prototypes were designed and built, including processor network interfaces for protected user-level communication. Recently, FORTH works on low-latency and high-bandwidth communication in chip multiprocessors and in scalable parallel processing and storage systems; work is at the hardware architecture and runtime system layers and their interactions.
Staff member
Prof. Manolis Katevenis received his PhD degree in Computer Science from U.C. Berkeley in 1983, where he was the chief implementer of the RISC II single-chip microprocessor (precursor of the SUN SPARC architecture); for this work he received the 1984 ACM Doctoral Dissertation Award. In 1984-85 he was Assistant Professor at Stanford University, and since 1986 he is with the Univ. of Crete, where he is currently Professor, and with FORTH where he heads the CARV Laboratory; see http://archvlsi.ics.forth.gr/~kateveni.
Tasks
Coordinator of the interconnects cluster, cluster meetings.
INRIA
INRIA is the main French research institute dedicated to information technology. It networks skills from the fields of information, computer science and technology from the entire French research system. Throughout its six research units in Rocquencourt, Rennes, Sophia Antipolis, Lyon-Grenoble, Nancy and Bordeaux-Lille-Saclay, INRIA has a workforce of 3,500 employees, distributed across 120 joint research projects; in addition to its academic output, INRIA has led to the creation of more than 80 start-ups.
The INRIA groups involved in HiPEAC are Saclay (Alchemy), Rennes (CAPS) and Lyon (CompSys). Most of the researchers involved in this project have a long history of collaborating together, several researchers having moved from one research unit to another, leading to cross-fertilization and merging of the different research topics and approaches.
The research in these INRIA groups covers a wide range of topics, from processor micro-architecture to compiler optimizations, programming paradigms and methodology issues. Our research groups have made significant contributions in memory and ILP improvement techniques. They are now targeting long-term multi-threaded/multi-core architectures from micro-architecture, compilation and programming model perspectives together. INRIA is also working on the practical implementation issues of iterative optimization. In terms of methodology, it is working on thermal modeling for multi-cores, and has significant efforts on compiler and simulation, platforms, and novel simulation approaches.
Staff member
Olivier Temam graduated from Ecole Centrale de Paris in 1990, and then he has obtained a PhD in Computer Science from University of Rennes in 1993. He has been Assistant Professor at University of Versailles from 1994 to 1999, and then Professor at University of Paris Sud until 2004. Since then, he has been a Senior Researcher at INRIA Futurs in Paris (Saclay), where he heads the Alchemy group. He is also an Adjunct Professor at Ecole Polytechnique where he teaches computer architecture. His research interests include processor architecture and simulation, program optimization, emerging technologies and their impact on long-term architecture and programming. He has been a visiting scientist at University of Illinois (US), University of Leiden (The Netherlands), and UPC (Spain).
He is regularly publishing in, and part of the Program Committees of, top conferences such as MICRO, ISCA, ASPLOS, HPCA, CASES, etc. Since 2002, 7 PhDs have defended under his supervision, one of them scoring the award for best French PhD in Computer Science. Olivier Temam has also actively participated to the creation of the European HiPEAC1 Network of Excellence, as a steering committee member, and he is now involved in several recent IST and FET projects.
Tasks
Leader of the research program work package, coordinator of the simulation platform cluster and the compilation platform cluster, website.
ARM
ARM designs the technology that lays at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM’s comprehensive product offering includes 16/32-bit RISC microprocessors, data engines, graphic processors, 3D processors, digital libraries, embedded memories, peripherals, software and development tools, as well as analog functions and high-speed connectivity products. Combined with the company’s broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. ARM Holdings plc [(LSE:ARM); (Nasdaq:ARMHY)], ranked by Dataquest as the number one semiconductor IP supplier in the world, emerged as a pre-eminent force in the semiconductor revolution. When ARM pioneered the concept of openly-licensable IP for the development of 32-bit RISC microprocessor-based SoCs in the early 1990s, it changed the dynamics of the semiconductor industry forever. By licensing, rather than manufacturing and selling its chip technology, the Company established a new business model that has redefined the way microprocessors are designed, produced and sold. More importantly, ARM has shaped a new era of next-generation electronics: ARM Powered microprocessors are pervasive in the electronic products we use, driving key functions in a variety of applications in diverse markets, including automotive, consumer entertainment, imaging, microcontrollers, networking, storage, security and wireless.
ARM licenses its IP to a network of Partners, which includes some of the world’s leading semiconductor and system companies, including 19 out of the top 20 semiconductor vendors worldwide. These partners utilize ARMs low-cost, power-efficient core designs to create and manufacture microprocessors, peripherals and SoC solutions. As the foundation of the company’s global technology network, these Partners have played a pivotal role in the widespread adoption of the ARM architecture and to date, ARM Partners have shipped more than 5 billion ARM microprocessor cores. To support and complement the company’s RISC microprocessor cores and SoC IP, ARM has developed a strong software capability. Partners have access to an unrivalled range of software-based IP, operating systems (OS) ports, software design and verification tools and physical layer-based IP. In this way, ARM provides Partners with a full portfolio of offerings that deliver significant risk reduction and faster time-to-market benefits.
Staff member
Emre Ozer is an R&D staff engineer at ARM since 2005. Before joining ARM, he worked in the Department of Computer Science in Trinity College Dublin, Ireland as a research fellow, and in Motorola Inc. as a computer architect at Star*Core Design Center in Atlanta. He received his Ph.D. in the Department of Electrical and Computer Engineering at North Carolina State University in 2001, and his B.Sc. and M.Sc. degrees from the Department of Computer Science and Engineering at Yildiz Technical University in Istanbul in 1993 and 1996, respectively. His research interests are high-performance low-power microarchitecture design, embedded systems, multithreading, and multi-cores and hardware compilation.
Tasks
Internships
IBM Israel Science and Technology Ltd
Over 600 individuals work at IBM Israel – Science and Technology; 30 percent of the technical staff has doctorate degrees in computer science, electrical engineering, mathematics or related fields. Employees are actively involved in teaching at Israeli higher education institutions and supervising post-graduate theses. Many employees have received IBM ISRAEL awards for achievements and excellence. The IBM Israel – Science and Technology Labs include the Haifa Research Lab (HRL), the Haifa Development Lab (HDL) and the Haifa Software Lab (HSL) in Rehovot. Haifa Research Lab is part of IBM ISRAEL’s Research Division centered at Yorktown T.J. Watson Research Center and is the biggest IBM ISRAEL Research lab outside US.
Since it first opened as the IBM ISRAEL Scientific Center in 1972, the IBM ISRAEL Haifa Research Lab has conducted decades of research that has been vital to IBM ISRAEL’s success. R&D projects are being executed today by HRL for IBM ISRAEL Labs in the USA, Canada and Europe in areas such as storage systems, verification technologies, multimedia, active management, information retrieval, programming environments, optimization technologies and life sciences.
In code optimization technologies, HRL focuses on a range of optimization problems, both in compilers and post-link optimization tools which take advantage of the underlying structure of modern VLIW and superscalar processors (e.g. PowerPC). Haifa's researchers contributed to IBM ISRAEL's proprietary technology components as well as to open source tools such as the GNU C Compiler (GCC). In the context of GCC, IBM ISRAEL Haifa has been involved in researching sophisticated optimization techniques such as global and local instruction scheduling, modulo scheduling, auto-vectorization, etc. Complementary to optimizing compilers, HRL developed post-link binary instrumentation and optimization technology, called FDPR-Pro. The FDPR-Pro tool uses the profiling information and the program global view to optimize the most frequently executed pieces of code, potentially at the expense of the rest of the program. This technology proved itself in a variety of market segments such as database engines, embedded software components, etc. Recently, the Haifa researchers started looking into new promising domains such as dynamic and adaptive monitoring and optimization of long running programs, architectures of media processors (e.g. DSPs) and related code optimization problems, exploitation of machine learning techniques for iterative optimization, etc.
Staff member
Dr. Bilha Mendelson has been a member of the Haifa Research Laboratory in Haifa for several years. She worked on avionic real-time systems at Elbit Ltd. before attending graduate school. In 1990 she joined the Haifa Research Laboratory. She has been developing compiler optimizations for compiler for DSP and also for the AS/400 optimizing translator. Currently she is a manager of the Code Optimization Technology department. She received a B.Sc. and M.Sc. in computer science from the Technion - Israel Institute of Technology, Haifa, and Ph.D. in computer engineering from the University of Massachusetts at Amherst. She holds several patents primarily in the area of code optimization. Her areas of interest include code optimization algorithms, compiler technology, computer architecture, and performance improvement issues.
Tasks
Industrial workshops
ST FRANCE
STMicroelectronics is the world’s fifth largest semiconductor company with net revenues of US$9.84 billion in 2008. The Company is the leading producer of application-specific analog chips and power conversion devices. It is the #1 supplier of semiconductors for the Industrial market, set-top box applications, and MEMS (micro-electromechanical systems) chips for portable and consumer devices, including game controllers and smart phones. ST also occupies leading positions in fields as varied as automotive integrated circuits (#3), chips for computer peripherals (#3), and the rapidly expanding market for MEMS overall (#5).
ST aims to be the leader in multimedia convergence and power applications, offering one of the world’s broadest product portfolios, including application-specific products containing a large proprietary IP (Intellectual Property) content and multi-segment products that range from discrete devices to high-performance microcontrollers, secure smart card chips and MEMS devices.
The Company provides solutions for a wide array of Digital Consumer applications, with a particular focus on set-top boxes, digital TVs and digital audio, including radio. In the Computer Peripherals arena, ST provides leading solutions in data storage, printing, visual display units, power management for PC motherboards, and power supplies. A wide range of ST’s ASSPs (Application Specific Standard Products) power sophisticated Automotive systems such as engine control, vehicle safety equipment, door modules, and in-car infotainment. The Company also supplies industrial integrated circuits (IC) for factory automation systems, chips for lighting, battery chargers and power supplies, as well as chips for advanced Secure Access applications. ST pioneered and continues to refine the use of platform-based design methodologies for complex ICs in demanding applications such as mobile multimedia, set-top boxes and computer peripherals. The balanced portfolio approach allows ST to address the needs of all microelectronics users, from global strategic customers for whom ST is the partner of choice, for major System-on-Chip (SoC) projects to local enterprises that need fully-supported general-purpose devices and solutions.
To maximize the benefit of scale that is becoming increasingly important in some semiconductor markets, ST completed the creation of two joint ventures in 2008. In the memory field, ST, Intel and Francisco Partners formed a new company, Numonyx, dedicated to providing non-volatile memory solutions, including NAND and NOR Flash memories as well as MCP (multi-chip package) memory solutions, for a wide variety of consumer and industrial applications. ST holds a 48% share in Numonyx.
ST has also been very active in the wireless arena. In mid 2008, ST and NXP combined their key wireless semiconductor operations in a joint venture, in which ST held 80%. In February 2009, ST acquired the minority stake from NXP and merged its wireless operations with Ericsson Mobile Platforms to create ST-Ericsson, a 50/50 joint venture focusing on semiconductors and platforms for mobile applications.
ST Grenoble is a multidivisional center of excellence and innovation, dedicated to development, promotion and industrialization of mobile and consumer embedded products and their applications. Central organizations in charge of embedded processor architectures, product and advanced compilers and tools are part of ST Grenoble design center.
Staff member
Christian Bertin, PhD, is director of the Compiler Expertise Center at STMicroelectronics. He has a PhD from Institut National Polytechnique de Grenoble, in dynamic compilation and optimization. He is a graduated engineer from Ecole Nationale Superieure des Mines de Saint-Etienne, with a speciality in computer systems and networks. At EMSE, he led the Logic Programming and Expert Systems team in the computer laboratory (3 PhDs) and created a specialized software engineering cursus, called "Annee Speciale d'Informatique Genie Logiciel" dedicated to graduated engineers and masters, still in place today. In 1990, he joined the Advanced Computer Research Institute start-up (Lyon, Brussels), where he led the compiler group to produce the FORTRAN-90 optimizing compiler and the system C compilers and tools for the ACRI1 supercomputer decoupled architecture. He has been working in STMicroelectronics for 13 years and has created the Compiler Expertise Center (CEC) from scratch. CEC is in charge of product compilers, tools and libraries for most processor cores used in ST SoC products. The group is about 30 expert engineers developing compilation tools for various types of architectures (MCU, RISC, VLIW, reconfigurable cores) with a very strong software engineering (e.g. automated continuous integration, formal flows from architecture descriptions to compilers and tools, high quality assurance). Most CEC products rely on open source technologies like the Open64 compiler, GNU technologies, Newlib and on its own compiler back-end technology (LAO), itself based on the most advanced SSA and scheduling techniques, developed in cooperation with french laboratories. The group is also developing processor virtualization solutions based on .NET CIL, GCC4NET, Mono and its own Portable Virtual machine (PVM) in cooperation with HiPEAC partners or affiliated members
Tasks
HiPEAC start-ups