3rd HiPEAC Industrial Workshop

From 1st Jan 70

April 17, 2007
Organized by IBM Research Lab in Haifa, Israel
Registration

The Industrial Workshop will be coinciding with the next HiPEAC Cluster Meetings

Click here to request a traveling grant.

Agenda

09:15Arrival
09:30Welcome
Oded Cohn, Director, IBM HRL
Session 1: Making better use of Hardware
09:45
Initial Results on the Performance Implications of Thread Migration on a Chip Multi-Core
Y. Sazeides*, P. Michaud+, L. He*, D. Fetis+, C. Ioannou*, P. Charalambous* and A. Seznec+
*University of Cyprus, Nicosia, Cyprus, +Irisa-Inria, Rennes, France
10:15
Caravela: A Distributed Stream-Based Computing Platform
Leonel Sousa and Shinichi Yamagiwa, INESC-ID/IST, TULisbon
10:45
Probabilistic Cache Filtering
Yoav Etsion and Dror G. Feitelson (Hebrew University, Jerusalem)
11:15Coffee break
Session 2: Compiler Optimizations
11:35
Data Layout Optimizations in GCC
Olga Golovanevsky and Razya Ladelsky (IBM HRL)
12:05
SIMDinator: use of the x86 SIMD instructions
David Livshin (DALsoft)
12:35
Issues and challenges in compiling for multiple forms of parallelism, in IBM research compilers
Kathryn O'Brien (IBM T.J. Watson Research Center)
13:05Lunch (and informal discussions)
14:10
Keynote speech: Cell: a highly programmable C/GPU
Peter Hofstee, IBM Distinguished Engineer, chief architect of the Cell Synergistic Processor, and Cell chief scientist
15:00
Implementation and validation of a Cell simulator using UNISIM
Felipe Cabarcas, Alejandro Rico, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguade (UPC)
15:30Coffee break
Session 3: Making better use of Parallelism
15:50
CAPSULE: Parallel Execution of Component-Based Programs
Pierre Palatin, Zheng Li, Yves Lhuillier, Olivier Temam (INRIA)
16:20
Using Extremely Fine Granularity Multithreading for Energy Efficient Computing
Alex Gontmakher, Avi Mendelson and Assaf Schuster (Technion)
16:50
How many cores is too many cores
Avi Mendelson (Intel)
17:20 Concluding Remarks
David Bernstein (IBM HRL)
 SC dinner