UNISIM Environment Tutorial
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Date: January 28 2007
Duration: Full day tutorial
Location: Ghent, Belgium colocated with the 2nd HiPEAC Conference (January 28 to 30)
Schedule: 9:00 to 12:00 and 14:00 to 17:30 (see detailed schedule below)
What is UNISIM ?
UNISIM is a structural simulation environment which provides an intuitive mapping from the hardware block diagram to the simulator; each hardware block corresponds to a simulation module.
UNISIM is also a public repository where researchers will be able to download and upload (contribute) modules.
Why should I use UNISIM ?
UNISIM allows to reuse, exchange and compare simulator parts (and architecture ideas), something that is badly needed in academic research, and between academia and industry. This is awfully difficult to do with most current simulators, including SystemC-based ones.
How is that different from SystemC ?
SystemC is a good first step, as it promotes structural simulation, but it is not enough. SystemC similarly suggests to map hardware blocks to simulator modules, but forgets that hardware control, which corresponds to the least amount of transistors, corresponds to the highest amount of simulator lines. As a result, the intuition is good but reuse cannot really occur in practice.
UNISIM is focused on reuse of control code, provides a standardized module communication protocol and a control abstraction for that purpose. However, there is no contradiction between UNISIM and SystemC, UNISIM is more like a layer on top of SystemC.
Do I need to drop my current simulation tools ?
No, we take a realistic approach and UNISIM is designed from the ground up to be interoperable with existing simulators, from industry & academia. We achieve interoperability by wrapping full simulators or simulator parts. We have an example full SimpleScalar simulator stripped of its memory, wrapped into a UNISIM module, and talking to a UNISIM SDRAM module.
Moreover, UNISIM is in the process of developing a number of APIs (for power, GUI, functional simulators, sampling,…) which will allow third-party tools to be plugged into the UNISIM engine. We call these APIs simulator capabilities.
With upcoming CMPs, I need more a system-level simulator than a cycle-level one.
UNISIM provides two abstractions, one at the cycle-level (that is where we started), and a newer one at the system-level. Researchers are already developing simulators at both levels. The system-level is great for prototyping, the cycle-level for detailed evaluation.
Who are the UNISIM people anyway ?
UNISIM originated from the merging of the Liberty environment (Princeton University) and the MicroLib environment (INRIA, France), but it is now the official simulation platform of the European HiPEAC network, and other research groups, like UPC, Spain and CEA, France are now heavily involved. Because UNISIM already gathers several institutions and simulation environments, and we hope more later, it is an acronym for UNIted SIMulation environment.
What will we do in this tutorial ?
- We will present in more details the UNISIM simulation environment, what is currently available and what is on our roadmap.
- We will show how to design both cycle-level and system-level simulators.
- We will look into two existing examples: a cycle-level CMP simulator, and a system-level CMP simulator.
- We will do a number of hands-on so you get a better feeling of UNISIM (bring your laptop) if time permits.
Detailed schedule:
09:0010:30Basics of cycle-level simulation with UNISIM
10:3011:00Coffee break
11:0012:30Cycle level simulation with UNISIM & CMP Models
12:3014:00Lunch Break
14:0015:30Basics of TLM-level simulation
15:3016:00Coffee Break
16:0017:30Toward full system simulation
Contributors:
- David August, Princeton University, US (TBC)
- Sylvain Girbal, INRIA, France
- Daniel Gracia-Perez, CEA, France (TBC)
- Gilles Mouchard, CEA, France (TBC)
- Adrian Cristal, UPC, Spain (TBC)
- Olivier Temam, INRIA, France