Report of research results

Nowadays, the processor performance is being limited by the increasing gap between processor and memory speeds. A recent proposed architecture able to deal with these emerging large memory latencies is called Kilo-instruction processor, a combination of different mechanisms that makes the processor able to maintain thousands of in-flight instructions. Current multiprocessor systems also have to deal with this increasing memory latency while facing other sources of latencies: those coming from communication among processors. In this way, we propose the use of Kilo-instruction processors as computing nodes for small-scale CC-NUMA multiprocessors. We appropriately call this kind of systems Kilo-instruction Multiprocessors. In our first reduced evaluations of Kilo-instruction Multiprocessors good performance results are achieved since the great amount of in-flight instructions allows the system to hide the different latencies implicated, those coming from memory and network accesses.



What we propose with this project is to make an extensive evaluation of the Kilo-instruction Multiprocessors. The proposal is structured in three main parts.



1. An appropriate simulation infrastructure will be developed, making use of existing tools when available. This includes building-up a multiprocessor simulator where single processors will mimic the Kilo-instruction processor operation. Besides, these processors will be interconnected using a realistic interconnection network configuring a CC-NUMA multiprocessor system.



2. The simulation infrastructure developed will be evaluated. The evaluation methodology will comprise changing different interesting parameters, being the memory latency one of them. The benchmarks to be evaluated will also be an important issue of the work: numerical and commercial parallel applications have to be tested. The former ones, the numerical benchmarks, are chosen since most current multiprocessor systems are designed to perform better when running scientific and engineering workloads. On the other hand, when we talk about commercial benchmarks we refer specifically to database applications, and we choose those applications since today, they constitute a large and fast-growing segment of the market for multiprocessor servers.



3. The cache coherence protocol used in a CC-NUMA multiprocessor to keep the L2 caches coherent will be extensively analyzed in the context of a Kilo-instruction Multiprocessor. On the one hand, snoopy cache coherence protocols do not constitute a viable solution since they depend on an interconnection network with an ordered message delivery. On the other hand, traditional directory-based coherence protocols that keep a directory structure in main memory significantly increase the latency of L2 misses. We plan to study the effect that organizing the directory as a multilevel architecture has on these systems as well as novel speculative cache coherence protocols with lower latency than traditional ones.

Per Stenstrom and Jim Nilsson

- Stage: Barcelona 3 days/person (720 Euros)

- Travel: 1 round trip GOT-BCN/person (1600 Euros)



Mateo Valero, Adrian Cristal and Enric Morancho

- Stage: Gothenburg 3 days/person (1440 Euros)

- Travel: 1 round trip BCN-GOT/person (2400 Euros)



Marco Galluzzi

- Stage: Gothenburg 3 months (6000 Euros)

- Travel: 3 round trips BCN-GOT (2400 Euros)



Jose Garcia and Manuel Acacio

- Stage: Gothenburg 3 days/person (960 Euros)

Barcelona 2 days/person (480 Euros)

- Travel: 1 round trip ALC-GOT/person (1600 Euros)

1 round trip ALC-BCN/person (500 Euros)

Jim Nilsson (Chalmers)

Adrian Cristal (UPC)

Marco Galluzzi (UPC)

Manuel E. Acacacio (UMU)