HiPEAC Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip
CALL FOR PAPERS / CONTRIBUTIONS:
ADVANCE PROGRAM AND CALL FOR PARTICIPATION
Important Dates:
- Contribution registration (optional, desirable): 30 November 2006
- Extended Abstract submission deadline (PDF): 14 December 2006
- Author Notification: 04 January 2007
- Electronic version of text/slides (optional): 24-28 January 2007
- Workshop: Sunday 28 January 2007, afternoon, Ghent, Belgium, Co-located with the HiPEAC'07 International Conference on High Performance Embedded Architectures & Compilers
Aim of the Workshop:
The workshop aims at gathering together experts on on-chip and off-chip interconnects (especially from Europe), including both industry and academia, to discuss future trends, challenges, hot research topics, etc. It also aims at providing a forum for young researchers on this topic to present their work in progress in order to validate approaches, solutions, etc. without the pressure of having to complete all the work before being able to publish in a conference. The workshop will have no Proceedings, so submissions to it are not incompatible with submitting the work to other conferences.
Topics of Interest:
Embedded and other computation systems no longer operate in isolation, but are interconnected in various ways. While bus-based or wireless communication can be used in low-throughput applications, all new high-performance designs turn to switch-based interconnections using point-to-point links. This workshop concerns the architecture of interconnection switches or routers, and networks of switches or routers, whether on-chip or multi-chip; also of interest is the interfacing of these networks to the processors, memories, and accelarator engines. Topics of interest include:
- Networks-on-Chip (NoC)
- Multi-Chip Interconnection Networks, including Cluster Interconnects
- "Commodity Switches" as general-purpose building blocks
- Flow control and congestion management in switching fabrics
- Switching, buffering, and routing architectures
- Network interfaces, interprocessor communication primitives
- Virtualization
- Reliability, availability, fault tolerance
- Area/power versus functionality/QoS support in NoC architectures
- Design space exploration
- Network Service: debugging, embedded testing, power management, etc.
Submission:
Submissions and acceptance will be based on extended abstracts:
- Prospective contributors are urged to contact the Workshop Organizer, prof. Manolis Katevenis, by email to kateveni at ics.forth.gr, as soon as possible and preferably before the end of November 2006, giving a tentative title for their contribution.
- Please submit an extended abstract of 1 to 3 pages, in PDF format, by email to the Workshop Organizer as above, by the deadline of Thursday 14 December 2006 (strict deadline --no extensions).
- Notification of acceptance will be given by 4 January 2007.
- There will be no formal Proceedings, so submission to this Workshop is not incompatible with submitting the work to other conferences. However, authors are encouraged to send PDF files with their slides and/or text, a few days before the workshop (preferably by Wed. 24/1), to the Workshop Organizer, who will distribute them on-line to the participants at the Workshop.
Workshop Organizer:
Manolis Katevenis, FORTH and University of Crete, Greece
Program Committee:
- Ramon Beivide, Universidad de Cantabria, Spain
- Andrea Bianco, Politecnico di Torino, Italy
- Rafael Casado, Universidad de Castilla La Mancha, Spain
- Giuseppe Desoli, ST Microelectronics, Switzerland
- Jose Duato, Universidad Politecnica de Valencia, Spain
- Ran Ginosar, Technion, Israel
- Kees Goossens, NXP Semiconductors (formerly Philips), Netherlands
- Chris Jesshope, University of Amsterdam, Netherlands
- Ian Johnson, Xyratex Technology Ltd., United Kingdom
- Wojciech Kabacinski, Poznan University of Technology, Poland
- Ronald Luijten, IBM Zurich Research Laboratory, Switzerland
- Olav Lysne, Simula Research Lab and University of Oslo, Norway
- Cyriel Minkenberg, IBM Zurich Research Laboratory, Switzerland