This cluster extends cluster #355 (“Energy-efficient single-core processor design”). The previous cluster was exploratory in order to setup a collaboration between both research groups (Murcia and Patras) which resulted in a recently published paper in the Computing Frontiers Conference’07 [1].

Continuing with the previous work context, we can observe that advances in semiconductor technology will lead to more powerful CMP architectures in the future in order to support high performance demanding applications such as real-time media processing, parallel computing, high-speed networking, etc. In other domains such as battery-operated devices we can also devise an ever-increasing performance trend that makes these devices capable of supporting rich multimedia applications coupled with streaming on-demand audio and video. This increase in performance comes, again, along with increasing power demands.

Keeping the processor below a guaranteed power consumption level can be beneficial for battery life, an important factor that makes a mobile device attractive to consumers. Under certain circumstances, limiting power consumption may lead to performance degradation since the processor is forced to do less work in a given time window. Power constraints are also encountered in stationary devices. Having a predefined power budget, which is well respected, leads to a well predicted thermal density. This means that we can easily “a priori” set the thermal standards, thus accommodate costs related to temperature removal such as heat sinks, etc. However, the problem of enforcing a core- or chip-level power budget (at minimal performance cost) has not been studied at great depth so far in the literature.

Current research works aim at reducing power consumption with minimum performance impact. Some proposals employ DVFS (Dynamic Voltage and Frequency Scaling) techniques which have demonstrated promising results by reducing energy consumption during periods of inactivity. Power management DVFS-based approaches rely on fast voltage and frequency changes. However, they require fast DC-to-DC regulators and fast PLL re-synchronization, incurring in long transition delays (e.g., 10mV/microsecs) leading to long transition overheads. Furthermore, DVFS techniques rely on a very coarse executing window (on the order of microseconds) which makes DVFS only feasible with periods over 100K cycles (i.e., 100 microsecs for a 1 GHz system) in order to amortize the DVFS overhead.

As a result, DVFS-based power management policies may miss opportunities that can indeed lead to the reduction of power but at a higher performance cost. DVFS-based approaches cannot exploit situations such as instruction slack, instruction criticality or low confidence on the predicted path, in order to minimize performance degradation given a power budget. Conversely, we propose a micro-architectural approach based on both processor throttling techniques and dynamic resource reconfiguration which is a fine-grained approach that may lead to successfully drive the processor under the required power budget while not hurting performance as much as DVFS-based approaches.

[1] Juan M. Cebrian, Juan L. Aragon, Jose M. Garcia and Stefanos Kaxiras. “Adaptive VP Decay: Making Value Predictors Leakage-efficient Designs for High Performance Processors”.
In Proc. of the 4th ACM Int. Conference on Computing Frontiers (CF), Ischia, Italy, May 2007.

For this cluster we are requesting travel money for the following visits:

1) 6-week stay at the University of Patras (1 PhD student, Juan Manuel Cebrian)
1000 €: 1 round trip Murcia-Patras
1500 €: living expenses for the 6-week period (room rental and maintenance)

2) 10-day visit to the University of Murcia (1 researcher, Stefanos Kaxiras)
1000 €: 1 round trip Patras-Murcia
1500 €: hotel accommodation and maintenance

3) 10-day visit to the University of Patras (1 researcher, Juan Luis Aragón)
1000 €: 1 round trip Murcia-Patras
1500 €: hotel accommodation and maintenance

Juan Manuel Cebrian (Ph.D. student)